From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mailman by lists.gnu.org with tmda-scanned (Exim 4.43) id 1LZ1g8-0000w8-KA for qemu-devel@nongnu.org; Mon, 16 Feb 2009 06:30:24 -0500 Received: from exim by lists.gnu.org with spam-scanned (Exim 4.43) id 1LZ1g6-0000u0-J4 for qemu-devel@nongnu.org; Mon, 16 Feb 2009 06:30:23 -0500 Received: from [199.232.76.173] (port=44778 helo=monty-python.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1LZ1g6-0000tx-DV for qemu-devel@nongnu.org; Mon, 16 Feb 2009 06:30:22 -0500 Received: from lizzard.sbs.de ([194.138.37.39]:24924) by monty-python.gnu.org with esmtps (TLS-1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.60) (envelope-from ) id 1LZ1g5-00063g-Sh for qemu-devel@nongnu.org; Mon, 16 Feb 2009 06:30:22 -0500 Received: from mail1.sbs.de (localhost [127.0.0.1]) by lizzard.sbs.de (8.12.11.20060308/8.12.11) with ESMTP id n1GBUGqn007831 for ; Mon, 16 Feb 2009 12:30:18 +0100 Received: from [139.25.109.167] (mchn012c.mchp.siemens.de [139.25.109.167] (may be forged)) by mail1.sbs.de (8.12.11.20060308/8.12.11) with ESMTP id n1GBUEuf015053 for ; Mon, 16 Feb 2009 12:30:16 +0100 Message-ID: <49994E46.1030802@siemens.com> Date: Mon, 16 Feb 2009 12:30:14 +0100 From: Jan Kiszka MIME-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-15 Content-Transfer-Encoding: 7bit Subject: [Qemu-devel] [PATCH] arm: Fix gic_irq_state.level bitfield type Reply-To: qemu-devel@nongnu.org List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel Found while cleaning up compiler warnings: GIC_*_LEVEL macros strongly suggest that gic_irq_state.level is intended to be per-CPU and not just a single, global bit. I'm unable to test the effect, but it seems to be the most reasonable fix for the apparent brokenness. Signed-off-by: Jan Kiszka --- hw/arm_gic.c | 2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/hw/arm_gic.c b/hw/arm_gic.c index fef3113..8e61b6e 100644 --- a/hw/arm_gic.c +++ b/hw/arm_gic.c @@ -39,7 +39,7 @@ typedef struct gic_irq_state unsigned enabled:1; unsigned pending:NCPU; unsigned active:NCPU; - unsigned level:1; + unsigned level:NCPU; unsigned model:1; /* 0 = N:N, 1 = 1:N */ unsigned trigger:1; /* nonzero = edge triggered. */ } gic_irq_state;