From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mailman by lists.gnu.org with tmda-scanned (Exim 4.43) id 1LsJFs-0003fy-7E for qemu-devel@nongnu.org; Fri, 10 Apr 2009 12:07:00 -0400 Received: from exim by lists.gnu.org with spam-scanned (Exim 4.43) id 1LsJFq-0003ec-MT for qemu-devel@nongnu.org; Fri, 10 Apr 2009 12:06:59 -0400 Received: from [199.232.76.173] (port=36745 helo=monty-python.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1LsJFq-0003eW-GO for qemu-devel@nongnu.org; Fri, 10 Apr 2009 12:06:58 -0400 Received: from hall.aurel32.net ([88.191.82.174]:40440) by monty-python.gnu.org with esmtps (TLS-1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.60) (envelope-from ) id 1LsJFp-0003uf-WF for qemu-devel@nongnu.org; Fri, 10 Apr 2009 12:06:58 -0400 Message-ID: <49DF6E9A.7060300@aurel32.net> Date: Fri, 10 Apr 2009 18:06:50 +0200 From: Aurelien Jarno MIME-Version: 1.0 Subject: Re: [Qemu-devel] [RFC][PATCH] tcg: allocate memory to spill registers on startup References: <20090410085406.GA15094@volta.aurel32.net> <200904101620.10589.paul@codesourcery.com> <49DF664E.2080607@aurel32.net> <200904101652.31884.paul@codesourcery.com> In-Reply-To: <200904101652.31884.paul@codesourcery.com> Content-Type: text/plain; charset=ISO-8859-15 Content-Transfer-Encoding: 8bit Reply-To: qemu-devel@nongnu.org List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Paul Brook Cc: qemu-devel@nongnu.org Paul Brook a écrit : >> I am trying to fix the following comment from Fabrice (tcg.c) >> >> /* XXX: for load/store we could do that only for the slow path >> (i.e. when a memory callback is called) */ >> >> The idea is not to do register allocation/spilling in tcg-target.c, but >> to save registers containing TCG globals to memory in the slow path only >> and without touching the TCGTemp structure. That's why it has to be done >> in tcg-target.c > > Hmm, you don't actually have to allocate a slot, just you need to stash the > values somewhere while you're making the slow call, then restore them > afterwards. The bits that do need writing back to home locations (i.e. > visible guest cpu state) already have memory locations. For TCG globals, that's true. But the plan is also to reduce the list of clobbered registers when the fast path is taken (e.g. only 2 registers are used by the load/store code on x86_64). This means that the other clobbered registers according to the ABI have to be saved/restored when taking the slow path. This looks like the best location to save those registers. -- Aurelien Jarno GPG: 1024D/F1BCDB73 aurelien@aurel32.net http://www.aurel32.net