From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mailman by lists.gnu.org with tmda-scanned (Exim 4.43) id 1LzZEy-0005ZG-DG for qemu-devel@nongnu.org; Thu, 30 Apr 2009 12:36:04 -0400 Received: from exim by lists.gnu.org with spam-scanned (Exim 4.43) id 1LzZEt-0005WJ-F1 for qemu-devel@nongnu.org; Thu, 30 Apr 2009 12:36:03 -0400 Received: from [199.232.76.173] (port=58110 helo=monty-python.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1LzZEt-0005WA-8V for qemu-devel@nongnu.org; Thu, 30 Apr 2009 12:35:59 -0400 Received: from e1.ny.us.ibm.com ([32.97.182.141]:39002) by monty-python.gnu.org with esmtps (TLS-1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.60) (envelope-from ) id 1LzZEs-0008AC-UV for qemu-devel@nongnu.org; Thu, 30 Apr 2009 12:35:59 -0400 Received: from d01relay04.pok.ibm.com (d01relay04.pok.ibm.com [9.56.227.236]) by e1.ny.us.ibm.com (8.13.1/8.13.1) with ESMTP id n3UGWPol011055 for ; Thu, 30 Apr 2009 12:32:25 -0400 Received: from d01av03.pok.ibm.com (d01av03.pok.ibm.com [9.56.224.217]) by d01relay04.pok.ibm.com (8.13.8/8.13.8/NCO v9.2) with ESMTP id n3UGZvOt141764 for ; Thu, 30 Apr 2009 12:35:57 -0400 Received: from d01av03.pok.ibm.com (loopback [127.0.0.1]) by d01av03.pok.ibm.com (8.12.11.20060308/8.13.3) with ESMTP id n3UGZveD026216 for ; Thu, 30 Apr 2009 12:35:57 -0400 Message-ID: <49F9D36B.8040600@us.ibm.com> Date: Thu, 30 Apr 2009 11:35:55 -0500 From: Anthony Liguori MIME-Version: 1.0 References: <20090430161508.GA15893@redhat.com> In-Reply-To: <20090430161508.GA15893@redhat.com> Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Subject: [Qemu-devel] Re: questions on default_config_write in hw/pci.c List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: "Michael S. Tsirkin" Cc: Marcelo Tosatti , Avi Kivity , qemu-devel@nongnu.org I can only answer some of this.. Michael S. Tsirkin wrote: > Hi, > I've been looking at hw/pci.c, specifically at how config > read/write are implemented, and have a couple of questions > about default_config_write: > > 1. The code at the beginning (if len == 4 ...) > seems to only update pci base registers if a dword write > is performed. I think it's legal for the guest to perform 4 > single-byte writes. Should this be supported? > > 2. The large switch statement at the end of this function > uses hard-coded register offsets. Would it make sense > to change it to use macros from hw/pci.h? > Yes. > 3. Still there I see: > switch(d->config[0x0e]) { > case 0x00: > case 0x80: > register 0x0e is header type, which has defined values > of 0x00 (device or host bridge), 0x01 (pci to pci bridge) and > 0x02 (cardbus bridge). What is 0x80 and when is it used? > Would it make sense to remove this? > > 4. Still there, there's some handling done for type 1 devices. > This support seems imcomplete. > Are there any PCI-to-PCI bridges emulated by qemu? > Would it make sense to remove this code? > PCI-to-PCI bridges are used on non-x86 machine types by default. Presumably, they work enough for those boards. I've tried to use a PCI bridge in an x86 machine type but it's not very functional (IIRC, it didn't work for devices in any slot other than 0). -- Regards, Anthony Liguori