From: Richard Henderson <richard.henderson@linaro.org>
To: qemu-devel@nongnu.org
Subject: Re: [PATCH 2/4] linux-user/riscv: Add extended state to sigcontext
Date: Wed, 3 Sep 2025 07:31:57 +0200 [thread overview]
Message-ID: <49bf5320-37c9-4632-9165-0ced917ea64e@linaro.org> (raw)
In-Reply-To: <20250903042510.279954-3-npiggin@gmail.com>
On 9/3/25 06:25, Nicholas Piggin wrote:
> static void restore_sigcontext(CPURISCVState *env, struct target_sigcontext *sc)
> {
> + struct target_ctx_hdr *hdr;
> int i;
>
> - __get_user(env->pc, &sc->pc);
> + __get_user(env->pc, &sc->sc_regs.pc);
>
> for (i = 1; i < 32; ++i) {
> - __get_user(env->gpr[i], &sc->gpr[i - 1]);
> + __get_user(env->gpr[i], &sc->sc_regs.gpr[i - 1]);
> }
> for (i = 0; i < 32; ++i) {
> - __get_user(env->fpr[i], &sc->fpr[i]);
> + __get_user(env->fpr[i], &sc->sc_fpregs.fpr[i]);
> }
>
> uint32_t fcsr;
> - __get_user(fcsr, &sc->fcsr);
> + __get_user(fcsr, &sc->sc_fpregs.fcsr);
> riscv_csr_write(env, CSR_FCSR, fcsr);
> +
> + hdr = &sc->sc_extdesc.hdr;
> + uint32_t rsv;
> + __get_user(rsv, &sc->sc_extdesc.reserved);
> + if (rsv != 0) {
> + qemu_log_mask(LOG_GUEST_ERROR, "signal: sigcontext reserved field is "
> + "non-zero. Attempting restore anyway.");
> + }
The kernel returns -EINVAL from restore_sigcontext, which causes rt_sigreturn to
force_sig(SIGSEGV). We don't need -ERRNO here, but returning bool success would be proper.
r~
next prev parent reply other threads:[~2025-09-03 5:32 UTC|newest]
Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-09-03 4:25 [PATCH 0/4] linux-user/riscv: add vector state to signal Nicholas Piggin
2025-09-03 4:25 ` [PATCH 1/4] tests/tcg/riscv64: Add a user signal handling test Nicholas Piggin
2025-09-03 4:25 ` [PATCH 2/4] linux-user/riscv: Add extended state to sigcontext Nicholas Piggin
2025-09-03 5:31 ` Richard Henderson [this message]
2025-09-03 4:25 ` [PATCH 3/4] linux-user/riscv: Add vector state to signal context Nicholas Piggin
2025-09-03 9:14 ` Richard Henderson
2025-09-03 4:25 ` [PATCH 4/4] tests/tcg/riscv64: Add vector state to signal test Nicholas Piggin
2025-09-03 20:15 ` Daniel Henrique Barboza
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