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From: Pierrick Bouvier <pierrick.bouvier@linaro.org>
To: "Philippe Mathieu-Daudé" <philmd@linaro.org>,
	"Tao Tang" <tangtao1634@phytium.com.cn>,
	qemu-arm@nongnu.org, qemu-devel@nongnu.org
Cc: Eric Auger <eric.auger@redhat.com>,
	Peter Maydell <peter.maydell@linaro.org>,
	Chen Baozi <chenbaozi@phytium.com.cn>,
	smostafa@google.com, jean-philippe@linaro.org
Subject: Re: [RFC 00/11] hw/arm/smmuv3: Add initial support for Secure State
Date: Tue, 12 Aug 2025 10:50:54 -0700	[thread overview]
Message-ID: <49d2568d-8f15-4cc5-8295-b02540890be9@linaro.org> (raw)
In-Reply-To: <805a9a58-df34-4a0c-8613-1c7f22310170@linaro.org>

On 8/11/25 3:26 AM, Philippe Mathieu-Daudé wrote:
> On 10/8/25 18:11, Tao Tang wrote:
>>
>> On 2025/8/7 05:28, Pierrick Bouvier wrote:
>>> On 8/6/25 8:11 AM, Tao Tang wrote:
> 
> 
>>>> Secure Translation Path: Since the TF-A SMMUv3 Test Engine does not
>>>> support QEMU, and no secure device assignment feature exists yet, I
>>>> created a custom platform device to test the secure translation flow.
>>>> To trigger the translation logic, I initiated MMIO writes to this
>>>> device from within Hafnium. The device's MMIO callback handler then
>>>> performed DMA accesses via its IOMMU region, exercising the secure
>>>> translation path. While SMMUv3 is typically used for PCIe on
>>>> physical SoCs, the architecture allows its use with platform devices
>>>> via a stream-id binding in the device tree. The test harness
>>>> required some non-standard modifications to decouple the SMMU from
>>>> its tight integration with PCIe. The code for this test device is
>>>> available for review at [3]. README.md with detailed instructions is
>>>> also provided.
>>>>
>>>
>>> I am not sure about the current policy in QEMU for test oriented
>>> devices, but it would be really useful to have something similar
>>> upstream (Note: it's out of the scope of this series).
>>> One challenge working with SMMU emulation is that reproducing setups
>>> and triggering specific code paths is hard to achieve, due to the
>>> indirect use of SMMU feature (through DMA) and the complex software
>>> stack usually involved.
>>> Having something upstream available to work on SMMU emulation, at
>>> least on device side, would be a great addition.
>>>
>>> Eric, Peter, is this something that would be acceptable to merge?
> 
> 
> This shouldn't be an issue, we already have some:
> 
> $ git ls-files|fgrep testdev
> chardev/testdev.c
> docs/specs/pci-testdev.rst
> hw/hyperv/hyperv_testdev.c
> hw/misc/pc-testdev.c
> hw/misc/pci-testdev.c
> hw/tricore/tricore_testdevice.c
> 

Looks good indeed, and we have the TEST_DEVICES category for that.

> 
>> Looking ahead, my plan is to refactor the smmuv3-test platform device.
>> The goal is to make it self-contained within QEMU, removing the current
>> dependency on Hafnium to trigger its operations. I plan to submit this
>> as a separate RFC patch series in the next few days.
> 



  reply	other threads:[~2025-08-12 17:52 UTC|newest]

Thread overview: 47+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-08-06 15:11 [RFC 00/11] hw/arm/smmuv3: Add initial support for Secure State Tao Tang
2025-08-06 15:11 ` [RFC 01/11] hw/arm/smmuv3: Introduce secure registers and commands Tao Tang
2025-08-11 10:22   ` Philippe Mathieu-Daudé
2025-08-11 10:43     ` Philippe Mathieu-Daudé
2025-08-18 21:21   ` Mostafa Saleh
2025-08-06 15:11 ` [RFC 02/11] hw/arm/smmuv3: Implement read/write logic for secure registers Tao Tang
2025-08-06 21:53   ` Pierrick Bouvier
2025-08-10 16:54     ` Tao Tang
2025-08-12 17:12       ` Pierrick Bouvier
2025-08-18 21:24   ` Mostafa Saleh
2025-08-20 15:21     ` Tao Tang
2025-08-23 10:41       ` Mostafa Saleh
2025-09-11 15:27         ` Tao Tang
2025-09-15  9:14           ` Mostafa Saleh
2025-09-15  9:34             ` Eric Auger
2025-08-06 15:11 ` [RFC 03/11] hw/arm/smmuv3: Implement S_INIT for secure initialization Tao Tang
2025-08-18 21:26   ` Mostafa Saleh
2025-08-20 16:01     ` Tao Tang
2025-08-06 15:11 ` [RFC 04/11] hw/arm/smmuv3: Enable command processing for the Secure state Tao Tang
2025-08-06 21:55   ` Pierrick Bouvier
2025-08-10 16:59     ` Tao Tang
2025-08-11 10:34       ` Philippe Mathieu-Daudé
2025-08-12 17:27         ` Pierrick Bouvier
2025-08-12 17:39           ` Philippe Mathieu-Daudé
2025-08-12 18:42         ` Peter Maydell
2025-08-15  6:02           ` Tao Tang
2025-08-15 14:53             ` Peter Maydell
2025-08-17  3:46               ` Tao Tang
2025-08-06 15:11 ` [RFC 05/11] hw/arm/smmuv3: Support secure event queue and error handling Tao Tang
2025-08-11 10:41   ` Philippe Mathieu-Daudé
2025-08-06 15:11 ` [RFC 06/11] hw/arm/smmuv3: Plumb security state through core functions Tao Tang
2025-08-18 21:28   ` Mostafa Saleh
2025-08-20 16:25     ` Tao Tang
2025-08-23 10:43       ` Mostafa Saleh
2025-08-06 15:11 ` [RFC 07/11] hw/arm/smmuv3: Add separate address space for secure SMMU accesses Tao Tang
2025-08-06 15:11 ` [RFC 08/11] hw/arm/smmuv3: Enable secure-side stage 2 TLB invalidations Tao Tang
2025-08-06 15:11 ` [RFC 09/11] hw/arm/smmuv3: Make the configuration cache security-state aware Tao Tang
2025-08-06 15:11 ` [RFC 10/11] hw/arm/smmuv3: Differentiate secure TLB entries via keying Tao Tang
2025-08-06 21:11 ` [RFC 00/11] hw/arm/smmuv3: Add initial support for Secure State Pierrick Bouvier
2025-08-06 21:28 ` Pierrick Bouvier
2025-08-10 16:11   ` Tao Tang
2025-08-11 10:26     ` Philippe Mathieu-Daudé
2025-08-12 17:50       ` Pierrick Bouvier [this message]
2025-08-12 18:04     ` Pierrick Bouvier
2025-08-15  5:49       ` Tao Tang
2025-09-30  4:04         ` Tao Tang
2025-08-18 21:52 ` Mostafa Saleh

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