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Sat, 25 Jan 2025 09:52:50 -0800 (PST) Received: from [192.168.74.94] ([50.200.230.211]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-21da424d59dsm34527835ad.218.2025.01.25.09.52.49 for (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Sat, 25 Jan 2025 09:52:50 -0800 (PST) Message-ID: <49d2c367-b206-478f-89e9-935911cb7394@linaro.org> Date: Sat, 25 Jan 2025 09:52:48 -0800 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 37/76] target/arm: Define and use new write_fp_*reg_merging() functions To: qemu-devel@nongnu.org References: <20250124162836.2332150-1-peter.maydell@linaro.org> <20250124162836.2332150-38-peter.maydell@linaro.org> Content-Language: en-US From: Richard Henderson In-Reply-To: <20250124162836.2332150-38-peter.maydell@linaro.org> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Received-SPF: pass client-ip=2607:f8b0:4864:20::632; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x632.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On 1/24/25 08:27, Peter Maydell wrote: > For FEAT_AFP's FPCR.NEP bit, we need to programmatically change the > behaviour of the writeback of the result for most SIMD scalar > operations, so that instead of zeroing the upper part of the result > register it merges the upper elements from one of the input > registers. > > Provide new functions write_fp_*reg_merging() which can be used > instead of the existing write_fp_*reg() functions when we want this > "merge the result with one of the input registers if FPCR.NEP is > enabled" handling, and use them in do_fp3_scalar_with_fpsttype(). > > Note that (as documented in the description of the FPCR.NEP bit) > which input register to use as the merge source varies by > instruction: for these 2-input scalar operations, the comparison > instructions take from Rm, not Rn. > > We'll extend this to also provide the merging behaviour for > the remaining scalar insns in subsequent commits. > > Signed-off-by: Peter Maydell > --- > target/arm/tcg/translate-a64.c | 117 +++++++++++++++++++++++++-------- > 1 file changed, 91 insertions(+), 26 deletions(-) > > diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c > index d34672a8ba6..19a4ae14c15 100644 > --- a/target/arm/tcg/translate-a64.c > +++ b/target/arm/tcg/translate-a64.c > @@ -665,6 +665,68 @@ static void write_fp_sreg(DisasContext *s, int reg, TCGv_i32 v) > write_fp_dreg(s, reg, tmp); > } > > +/* > + * Write a double result to 128 bit vector register reg, honouring FPCR.NEP: > + * - if FPCR.NEP == 0, clear the high elements of reg > + * - if FPCR.NEP == 1, set the high elements of reg from mergereg > + * (i.e. merge the result with those high elements) > + * In either case, SVE register bits above 128 are zeroed (per R_WKYLB). > + */ > +static void write_fp_dreg_merging(DisasContext *s, int reg, int mergereg, > + TCGv_i64 v) > +{ > + if (!s->fpcr_nep) { > + write_fp_dreg(s, reg, v); > + return; > + } > + > + /* > + * Move from mergereg to reg; this sets the high elements and > + * clears the bits above 128 as a side effect. > + */ > + tcg_gen_gvec_mov(MO_64, fp_reg_offset(s, reg, MO_64), > + fp_reg_offset(s, mergereg, MO_64), > + 16, vec_full_reg_size(s)); I think this would be clearer with vec_full_reg_offset(), though the result is correct either way. Otherwise, Reviewed-by: Richard Henderson r~