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From: "Philippe Mathieu-Daudé" <philmd@linaro.org>
To: Anton Johansson <anjo@rev.ng>, qemu-devel@nongnu.org
Cc: pierrick.bouvier@linaro.org, alistair.francis@wdc.com,
	richard.henderson@linaro.org, palmer@dabbelt.com
Subject: Re: [PATCH v2 2/3] hw/riscv: Replace target_ulong uses
Date: Wed, 29 Oct 2025 19:01:38 +0100	[thread overview]
Message-ID: <49e7ca69-3477-40c8-aad3-f799d848ce7a@linaro.org> (raw)
In-Reply-To: <20251027-feature-single-binary-hw-v1-v2-2-44478d589ae9@rev.ng>

On 27/10/25 13:35, Anton Johansson wrote:
> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
> Signed-off-by: Anton Johansson <anjo@rev.ng>
> ---
>   hw/riscv/riscv-iommu.c | 6 ++++--
>   hw/riscv/riscv_hart.c  | 2 +-
>   2 files changed, 5 insertions(+), 3 deletions(-)
> 
> diff --git a/hw/riscv/riscv-iommu.c b/hw/riscv/riscv-iommu.c
> index b33c7fe325..f8656ec04b 100644
> --- a/hw/riscv/riscv-iommu.c
> +++ b/hw/riscv/riscv-iommu.c
> @@ -26,6 +26,8 @@
>   #include "migration/vmstate.h"
>   #include "qapi/error.h"
>   #include "qemu/timer.h"
> +#include "qemu/target-info.h"
> +#include "qemu/bitops.h"
>   
>   #include "cpu_bits.h"
>   #include "riscv-iommu.h"
> @@ -391,9 +393,9 @@ static int riscv_iommu_spa_fetch(RISCVIOMMUState *s, RISCVIOMMUContext *ctx,
>               const uint64_t va_mask = (1ULL << va_len) - 1;
>   
>               if (pass == S_STAGE && va_len > 32) {
> -                target_ulong mask, masked_msbs;
> +                uint64_t mask, masked_msbs;
>   
> -                mask = (1L << (TARGET_LONG_BITS - (va_len - 1))) - 1;
> +                mask = MAKE_64BIT_MASK(0, target_long_bits() - va_len + 1);
>                   masked_msbs = (addr >> (va_len - 1)) & mask;
>   
>                   if (masked_msbs != 0 && masked_msbs != mask) {
> diff --git a/hw/riscv/riscv_hart.c b/hw/riscv/riscv_hart.c
> index c7e98a4308..65d2c92018 100644
> --- a/hw/riscv/riscv_hart.c
> +++ b/hw/riscv/riscv_hart.c
> @@ -93,7 +93,7 @@ static bool csr_qtest_callback(CharBackend *chr, gchar **words)
>           g_assert(rc == 0);
>           csr_call(words[1], cpu, csr, &val);
>   
> -        qtest_sendf(chr, "OK 0 "TARGET_FMT_lx"\n", (target_ulong)val);
> +        qtest_sendf(chr, "OK 0 %"PRIx64"\n", val);
>   
>           return true;
>       }
> 

What about csr_call()?


  reply	other threads:[~2025-10-29 18:03 UTC|newest]

Thread overview: 13+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-10-27 12:35 [PATCH v2 0/3] single-binary: Prepare hw/riscv for single compilation Anton Johansson via
2025-10-27 12:35 ` [PATCH v2 1/3] hw/riscv: Use generic hwaddr for firmware addressses Anton Johansson via
2025-10-27 12:39   ` Philippe Mathieu-Daudé
2025-10-27 18:13     ` Anton Johansson via
2025-10-27 12:35 ` [PATCH v2 2/3] hw/riscv: Replace target_ulong uses Anton Johansson via
2025-10-29 18:01   ` Philippe Mathieu-Daudé [this message]
2025-10-30 12:32     ` Anton Johansson via
2025-10-30 12:52       ` Philippe Mathieu-Daudé
2025-10-30  4:10   ` Alistair Francis
2025-10-27 12:35 ` [PATCH v2 3/3] hw/riscv: Widen OpenSBI dynamic info struct Anton Johansson via
2025-10-27 12:42   ` Philippe Mathieu-Daudé
2025-10-28  7:25 ` [PATCH v2 0/3] single-binary: Prepare hw/riscv for single compilation Philippe Mathieu-Daudé
2025-10-29 21:56   ` Philippe Mathieu-Daudé

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