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Sat, 25 Jan 2025 09:08:26 -0800 (PST) Received: from [192.168.74.94] ([50.200.230.211]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-72f8a6b2cf6sm3910221b3a.49.2025.01.25.09.08.25 for (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Sat, 25 Jan 2025 09:08:26 -0800 (PST) Message-ID: <49f1651f-89f6-41ba-92cd-dac25b3eba14@linaro.org> Date: Sat, 25 Jan 2025 09:08:24 -0800 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 27/76] target/arm: Define FPCR AH, FIZ, NEP bits To: qemu-devel@nongnu.org References: <20250124162836.2332150-1-peter.maydell@linaro.org> <20250124162836.2332150-28-peter.maydell@linaro.org> Content-Language: en-US From: Richard Henderson In-Reply-To: <20250124162836.2332150-28-peter.maydell@linaro.org> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Received-SPF: pass client-ip=2607:f8b0:4864:20::62d; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On 1/24/25 08:27, Peter Maydell wrote: > The Armv8.7 FEAT_AFP feature defines three new control bits in > the FPCR: > * FPCR.AH: "alternate floating point mode"; this changes floating > point behaviour in a variety of ways, including: > - the sign of a default NaN is 1, not 0 > - if FPCR.FZ is also 1, denormals detected after rounding > with an unbounded exponent has been applied are flushed to zero > - FPCR.FZ does not cause denormalized inputs to be flushed to zero > - miscellaneous other corner-case behaviour changes > * FPCR.FIZ: flush denormalized numbers to zero on input for > most instructions > * FPCR.NEP: makes scalar SIMD operations merge the result with > higher vector elements in one of the source registers, instead > of zeroing the higher elements of the destination > > This commit defines the new bits in the FPCR, and allows them to be > read or written when FEAT_AFP is implemented. Actual behaviour > changes will be implemented in subsequent commits. > > Note that these are the first FPCR bits which don't appear in the > AArch32 FPSCR view of the register, and which share bit positions > with FPSR bits. > > Signed-off-by: Peter Maydell > --- > target/arm/cpu-features.h | 5 +++++ > target/arm/cpu.h | 3 +++ > target/arm/vfp_helper.c | 11 ++++++++--- > 3 files changed, 16 insertions(+), 3 deletions(-) > > diff --git a/target/arm/cpu-features.h b/target/arm/cpu-features.h > index 30302d6c5b4..7bf24c506b3 100644 > --- a/target/arm/cpu-features.h > +++ b/target/arm/cpu-features.h > @@ -802,6 +802,11 @@ static inline bool isar_feature_aa64_hcx(const ARMISARegisters *id) > return FIELD_EX64(id->id_aa64mmfr1, ID_AA64MMFR1, HCX) != 0; > } > > +static inline bool isar_feature_aa64_afp(const ARMISARegisters *id) > +{ > + return FIELD_EX64(id->id_aa64mmfr1, ID_AA64MMFR1, AFP) != 0; > +} > + > static inline bool isar_feature_aa64_tidcp1(const ARMISARegisters *id) > { > return FIELD_EX64(id->id_aa64mmfr1, ID_AA64MMFR1, TIDCP1) != 0; > diff --git a/target/arm/cpu.h b/target/arm/cpu.h > index 2213c277348..7ba227ac4c5 100644 > --- a/target/arm/cpu.h > +++ b/target/arm/cpu.h > @@ -1713,6 +1713,9 @@ void vfp_set_fpscr(CPUARMState *env, uint32_t val); > */ > > /* FPCR bits */ > +#define FPCR_FIZ (1 << 0) /* Flush Inputs to Zero (FEAT_AFP) */ > +#define FPCR_AH (1 << 1) /* Alternate Handling (FEAT_AFP) */ > +#define FPCR_NEP (1 << 2) /* SIMD scalar ops preserve elts (FEAT_AFP) */ > #define FPCR_IOE (1 << 8) /* Invalid Operation exception trap enable */ > #define FPCR_DZE (1 << 9) /* Divide by Zero exception trap enable */ > #define FPCR_OFE (1 << 10) /* Overflow exception trap enable */ > diff --git a/target/arm/vfp_helper.c b/target/arm/vfp_helper.c > index 3c8f3e65887..8c79ab4fc8a 100644 > --- a/target/arm/vfp_helper.c > +++ b/target/arm/vfp_helper.c > @@ -242,6 +242,9 @@ static void vfp_set_fpcr_masked(CPUARMState *env, uint32_t val, uint32_t mask) > if (!cpu_isar_feature(any_fp16, cpu)) { > val &= ~FPCR_FZ16; > } > + if (!cpu_isar_feature(aa64_afp, cpu)) { > + val &= ~(FPCR_FIZ | FPCR_AH | FPCR_NEP); > + } I suppose this aa64 check, without is_a64(), is ok because the a32 caller has already applied FPSCR_FPCR_MASK. And similarly for the ebf16 check below. > > if (!cpu_isar_feature(aa64_ebf16, cpu)) { > val &= ~FPCR_EBF; But it does feel like we could usefully move these to vfp_set_fpcr, or such? r~