From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mailman by lists.gnu.org with tmda-scanned (Exim 4.43) id 1M2XIo-0000ec-Dq for qemu-devel@nongnu.org; Fri, 08 May 2009 17:08:18 -0400 Received: from exim by lists.gnu.org with spam-scanned (Exim 4.43) id 1M2XIj-0000a0-KU for qemu-devel@nongnu.org; Fri, 08 May 2009 17:08:17 -0400 Received: from [199.232.76.173] (port=43555 helo=monty-python.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1M2XIj-0000Zt-EV for qemu-devel@nongnu.org; Fri, 08 May 2009 17:08:13 -0400 Received: from mx20.gnu.org ([199.232.41.8]:48919) by monty-python.gnu.org with esmtps (TLS-1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.60) (envelope-from ) id 1M2XIi-000588-S0 for qemu-devel@nongnu.org; Fri, 08 May 2009 17:08:13 -0400 Received: from e33.co.us.ibm.com ([32.97.110.151]) by mx20.gnu.org with esmtp (Exim 4.60) (envelope-from ) id 1M2XIi-0005D9-4z for qemu-devel@nongnu.org; Fri, 08 May 2009 17:08:12 -0400 Received: from d03relay02.boulder.ibm.com (d03relay02.boulder.ibm.com [9.17.195.227]) by e33.co.us.ibm.com (8.13.1/8.13.1) with ESMTP id n48L6ONl017010 for ; Fri, 8 May 2009 15:06:24 -0600 Received: from d03av02.boulder.ibm.com (d03av02.boulder.ibm.com [9.17.195.168]) by d03relay02.boulder.ibm.com (8.13.8/8.13.8/NCO v9.2) with ESMTP id n48L8AZS204572 for ; Fri, 8 May 2009 15:08:10 -0600 Received: from d03av02.boulder.ibm.com (loopback [127.0.0.1]) by d03av02.boulder.ibm.com (8.12.11.20060308/8.13.3) with ESMTP id n48L89Ci011616 for ; Fri, 8 May 2009 15:08:10 -0600 Message-ID: <4A049F37.3040603@us.ibm.com> Date: Fri, 08 May 2009 16:08:07 -0500 From: Anthony Liguori MIME-Version: 1.0 References: <1241419677.8815.42.camel@yhuang-dev.sh.intel.com> In-Reply-To: <1241419677.8815.42.camel@yhuang-dev.sh.intel.com> Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Subject: [Qemu-devel] Re: [RFC -v3 1/2] QEMU-KVM: MCE: Add MCE simulation to qemu/tcg List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Huang Ying Cc: "kvm@vger.kernel.org" , Andi Kleen , Avi Kivity , qemu-devel@nongnu.org Huang Ying wrote: > - MCE features are initialized when VCPU is intialized according to CPUID. > - A monitor command "mce" is added to inject a MCE. > - A new interrupt mask: CPU_INTERRUPT_MCE is added to inject the MCE. > > Signed-off-by: Huang Ying > > --- > cpu-all.h | 4 ++ > cpu-exec.c | 4 ++ > monitor.c | 49 +++++++++++++++++++++++++++++++++ > target-i386/cpu.h | 22 +++++++++++++++ > target-i386/helper.c | 70 ++++++++++++++++++++++++++++++++++++++++++++++++ > target-i386/op_helper.c | 34 +++++++++++++++++++++++ > 6 files changed, 183 insertions(+) > > --- a/target-i386/cpu.h > +++ b/target-i386/cpu.h > @@ -202,6 +202,7 @@ > #define CR4_DE_MASK (1 << 3) > #define CR4_PSE_MASK (1 << 4) > #define CR4_PAE_MASK (1 << 5) > +#define CR4_MCE_MASK (1 << 6) > #define CR4_PGE_MASK (1 << 7) > #define CR4_PCE_MASK (1 << 8) > #define CR4_OSFXSR_SHIFT 9 > @@ -248,6 +249,17 @@ > #define PG_ERROR_RSVD_MASK 0x08 > #define PG_ERROR_I_D_MASK 0x10 > > +#define MCE_CAP_DEF 0x100 > +#define MCE_BANKS_DEF 4 > + > +#define MCG_CTL_P (1UL<<8) > + > +#define MCG_STATUS_MCIP (1UL<<2) > + > +#define MCI_STATUS_VAL (1UL<<63) > +#define MCI_STATUS_OVER (1UL<<62) > +#define MCI_STATUS_UC (1UL<<61) > + > #define MSR_IA32_TSC 0x10 > #define MSR_IA32_APICBASE 0x1b > #define MSR_IA32_APICBASE_BSP (1<<8) > @@ -288,6 +300,11 @@ > > #define MSR_MTRRdefType 0x2ff > > +#define MSR_MC0_CTL 0x400 > +#define MSR_MC0_STATUS 0x401 > +#define MSR_MC0_ADDR 0x402 > +#define MSR_MC0_MISC 0x403 > + > #define MSR_EFER 0xc0000080 > > #define MSR_EFER_SCE (1 << 0) > @@ -674,6 +691,11 @@ typedef struct CPUX86State { > user */ > struct APICState *apic_state; > uint32_t mp_state; > + > + uint64 mcg_cap; > + uint64 mcg_status; > + uint64 mcg_ctl; > + uint64 *mce_banks; > } CPUX86State; > > Doesn't this need to be added to the savevm/loadvm state? -- Regards, Anthony Liguori