From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mailman by lists.gnu.org with tmda-scanned (Exim 4.43) id 1M7wlP-0007VC-He for qemu-devel@nongnu.org; Sat, 23 May 2009 15:20:11 -0400 Received: from exim by lists.gnu.org with spam-scanned (Exim 4.43) id 1M7wlK-0007Ql-IL for qemu-devel@nongnu.org; Sat, 23 May 2009 15:20:10 -0400 Received: from [199.232.76.173] (port=35457 helo=monty-python.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1M7wlK-0007Qc-DD for qemu-devel@nongnu.org; Sat, 23 May 2009 15:20:06 -0400 Received: from fmmailgate03.web.de ([217.72.192.234]:52016) by monty-python.gnu.org with esmtp (Exim 4.60) (envelope-from ) id 1M7wlI-0006i1-Vn for qemu-devel@nongnu.org; Sat, 23 May 2009 15:20:06 -0400 Message-ID: <4A184C63.3090108@web.de> Date: Sat, 23 May 2009 21:20:03 +0200 From: Jan Kiszka MIME-Version: 1.0 References: <4A184C2D.7060205@web.de> In-Reply-To: <4A184C2D.7060205@web.de> Content-Type: multipart/signed; micalg=pgp-sha1; protocol="application/pgp-signature"; boundary="------------enig7F36BAA7B41300D3A7A242CC" Sender: jan.kiszka@web.de Subject: [Qemu-devel] [PATCH 2/2] Revert "Introduce reset notifier order" List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Anthony Liguori Cc: qemu-devel This is an OpenPGP/MIME signed message (RFC 2440 and 3156) --------------enig7F36BAA7B41300D3A7A242CC Content-Type: text/plain; charset=ISO-8859-15 Content-Transfer-Encoding: quoted-printable This reverts commit 8217606e6edb49591b4a6fd5a0d1229cebe470a9, we solved the original problem it addressed less invasively. Signed-off-by: Jan Kiszka --- hw/ac97.c | 2 +- hw/acpi.c | 2 +- hw/adb.c | 2 +- hw/apic.c | 2 +- hw/arm_boot.c | 2 +- hw/axis_dev88.c | 2 +- hw/cirrus_vga.c | 2 +- hw/cs4231.c | 2 +- hw/cs4231a.c | 2 +- hw/cuda.c | 2 +- hw/dma.c | 2 +- hw/dp8393x.c | 2 +- hw/eccmemctl.c | 2 +- hw/eepro100.c | 2 +- hw/es1370.c | 2 +- hw/escc.c | 4 ++-- hw/esp.c | 2 +- hw/etraxfs.c | 2 +- hw/etraxfs_timer.c | 2 +- hw/fdc.c | 2 +- hw/fw_cfg.c | 2 +- hw/g364fb.c | 2 +- hw/grackle_pci.c | 2 +- hw/heathrow_pic.c | 2 +- hw/hpet.c | 2 +- hw/hw.h | 2 +- hw/i8254.c | 2 +- hw/i8259.c | 2 +- hw/ide.c | 8 ++++---- hw/ioapic.c | 2 +- hw/iommu.c | 2 +- hw/lm832x.c | 2 +- hw/m48t59.c | 2 +- hw/mac_dbdma.c | 2 +- hw/mac_nvram.c | 2 +- hw/mips_jazz.c | 2 +- hw/mips_malta.c | 4 ++-- hw/mips_mipssim.c | 2 +- hw/mips_r4k.c | 2 +- hw/musicpal.c | 4 ++-- hw/nseries.c | 2 +- hw/omap1.c | 2 +- hw/omap2.c | 2 +- hw/openpic.c | 4 ++-- hw/parallel.c | 4 ++-- hw/pc.c | 4 ++-- hw/pckbd.c | 4 ++-- hw/pl181.c | 2 +- hw/ppc405_boards.c | 4 ++-- hw/ppc405_uc.c | 24 ++++++++++++------------ hw/ppc4xx_devs.c | 6 +++--- hw/ppc4xx_pci.c | 2 +- hw/ppc_newworld.c | 2 +- hw/ppc_oldworld.c | 2 +- hw/ppc_prep.c | 2 +- hw/ps2.c | 4 ++-- hw/rc4030.c | 2 +- hw/sbi.c | 2 +- hw/serial.c | 2 +- hw/slavio_intctl.c | 2 +- hw/slavio_misc.c | 2 +- hw/slavio_timer.c | 2 +- hw/sparc32_dma.c | 2 +- hw/sun4c_intctl.c | 2 +- hw/sun4m.c | 10 +++++----- hw/sun4u.c | 2 +- hw/tcx.c | 2 +- hw/tsc2005.c | 2 +- hw/tsc210x.c | 4 ++-- hw/unin_pci.c | 2 +- hw/usb-ohci.c | 2 +- hw/vga.c | 2 +- hw/virtio.c | 3 +-- kvm-all.c | 2 +- vl.c | 7 ++----- 75 files changed, 106 insertions(+), 110 deletions(-) diff --git a/hw/ac97.c b/hw/ac97.c index 288f428..0ff2941 100644 --- a/hw/ac97.c +++ b/hw/ac97.c @@ -1369,7 +1369,7 @@ int ac97_init (PCIBus *bus) pci_register_io_region (&d->dev, 0, 256 * 4, PCI_ADDRESS_SPACE_IO, a= c97_map); pci_register_io_region (&d->dev, 1, 64 * 4, PCI_ADDRESS_SPACE_IO, ac= 97_map); register_savevm ("ac97", 0, 2, ac97_save, ac97_load, s); - qemu_register_reset (ac97_on_reset, 0, s); + qemu_register_reset (ac97_on_reset, s); AUD_register_card ("ac97", &s->card); ac97_on_reset (s); return 0; diff --git a/hw/acpi.c b/hw/acpi.c index fccae69..ec3ae78 100644 --- a/hw/acpi.c +++ b/hw/acpi.c @@ -550,7 +550,7 @@ i2c_bus *piix4_pm_init(PCIBus *bus, int devfn, uint32= _t smb_io_base, =20 s->smbus =3D i2c_init_bus(NULL, "i2c"); s->irq =3D sci_irq; - qemu_register_reset(piix4_reset, 0, s); + qemu_register_reset(piix4_reset, s); =20 return s->smbus; } diff --git a/hw/adb.c b/hw/adb.c index cceb098..c57aeaa 100644 --- a/hw/adb.c +++ b/hw/adb.c @@ -122,7 +122,7 @@ ADBDevice *adb_register_device(ADBBusState *s, int de= vaddr, d->devreq =3D devreq; d->devreset =3D devreset; d->opaque =3D opaque; - qemu_register_reset((QEMUResetHandler *)devreset, 0, d); + qemu_register_reset((QEMUResetHandler *)devreset, d); d->devreset(d); return d; } diff --git a/hw/apic.c b/hw/apic.c index 10b8184..063e46e 100644 --- a/hw/apic.c +++ b/hw/apic.c @@ -927,7 +927,7 @@ int apic_init(CPUState *env) s->timer =3D qemu_new_timer(vm_clock, apic_timer, s); =20 register_savevm("apic", s->id, 2, apic_save, apic_load, s); - qemu_register_reset(apic_reset, 0, s); + qemu_register_reset(apic_reset, s); =20 local_apics[s->id] =3D s; return 0; diff --git a/hw/arm_boot.c b/hw/arm_boot.c index acfa67e..35f0130 100644 --- a/hw/arm_boot.c +++ b/hw/arm_boot.c @@ -203,7 +203,7 @@ void arm_load_kernel(CPUState *env, struct arm_boot_i= nfo *info) if (info->nb_cpus =3D=3D 0) info->nb_cpus =3D 1; env->boot_info =3D info; - qemu_register_reset(main_cpu_reset, 0, env); + qemu_register_reset(main_cpu_reset, env); } =20 /* Assume that raw images are linux kernels, and ELF images are not.= */ diff --git a/hw/axis_dev88.c b/hw/axis_dev88.c index 60b719b..506ef28 100644 --- a/hw/axis_dev88.c +++ b/hw/axis_dev88.c @@ -271,7 +271,7 @@ void axisdev88_init (ram_addr_t ram_size, cpu_model =3D "crisv32"; } env =3D cpu_init(cpu_model); - qemu_register_reset(main_cpu_reset, 0, env); + qemu_register_reset(main_cpu_reset, env); =20 /* allocate RAM */ phys_ram =3D qemu_ram_alloc(ram_size); diff --git a/hw/cirrus_vga.c b/hw/cirrus_vga.c index f0bb8d9..48f8960 100644 --- a/hw/cirrus_vga.c +++ b/hw/cirrus_vga.c @@ -3228,7 +3228,7 @@ static void cirrus_init_common(CirrusVGAState * s, = int device_id, int is_pci) s->vga.cursor_invalidate =3D cirrus_cursor_invalidate; s->vga.cursor_draw_line =3D cirrus_cursor_draw_line; =20 - qemu_register_reset(cirrus_reset, 0, s); + qemu_register_reset(cirrus_reset, s); cirrus_reset(s); register_savevm("cirrus_vga", 0, 2, cirrus_vga_save, cirrus_vga_load= , s); } diff --git a/hw/cs4231.c b/hw/cs4231.c index a5ba221..2266980 100644 --- a/hw/cs4231.c +++ b/hw/cs4231.c @@ -175,6 +175,6 @@ void cs_init(target_phys_addr_t base, int irq, void *= intctl) cs_io_memory =3D cpu_register_io_memory(0, cs_mem_read, cs_mem_write= , s); cpu_register_physical_memory(base, CS_SIZE, cs_io_memory); register_savevm("cs4231", base, 1, cs_save, cs_load, s); - qemu_register_reset(cs_reset, 0, s); + qemu_register_reset(cs_reset, s); cs_reset(s); } diff --git a/hw/cs4231a.c b/hw/cs4231a.c index d08d7c3..33c9460 100644 --- a/hw/cs4231a.c +++ b/hw/cs4231a.c @@ -656,7 +656,7 @@ int cs4231a_init (qemu_irq *pic) DMA_register_channel (s->dma, cs_dma_read, s); =20 register_savevm ("cs4231a", 0, 1, cs_save, cs_load, s); - qemu_register_reset (cs_reset, 0, s); + qemu_register_reset (cs_reset, s); cs_reset (s); =20 AUD_register_card ("cs4231a", &s->card); diff --git a/hw/cuda.c b/hw/cuda.c index 828ccf7..145aa9c 100644 --- a/hw/cuda.c +++ b/hw/cuda.c @@ -762,6 +762,6 @@ void cuda_init (int *cuda_mem_index, qemu_irq irq) s->adb_poll_timer =3D qemu_new_timer(vm_clock, cuda_adb_poll, s); *cuda_mem_index =3D cpu_register_io_memory(0, cuda_read, cuda_write,= s); register_savevm("cuda", -1, 1, cuda_save, cuda_load, s); - qemu_register_reset(cuda_reset, 0, s); + qemu_register_reset(cuda_reset, s); cuda_reset(s); } diff --git a/hw/dma.c b/hw/dma.c index c8ed6b0..b95407b 100644 --- a/hw/dma.c +++ b/hw/dma.c @@ -493,7 +493,7 @@ static void dma_init2(struct dma_cont *d, int base, i= nt dshift, register_ioport_read (base + ((i + 8) << dshift), 1, 1, read_cont, d); } - qemu_register_reset(dma_reset, 0, d); + qemu_register_reset(dma_reset, d); dma_reset(d); for (i =3D 0; i < ARRAY_SIZE (d->regs); ++i) { d->regs[i].transfer_handler =3D dma_phony_handler; diff --git a/hw/dp8393x.c b/hw/dp8393x.c index 5aa1211..4418409 100644 --- a/hw/dp8393x.c +++ b/hw/dp8393x.c @@ -892,7 +892,7 @@ void dp83932_init(NICInfo *nd, target_phys_addr_t bas= e, int it_shift, nic_receive, nic_can_receive, nic_clean= up, s); =20 qemu_format_nic_info_str(s->vc, nd->macaddr); - qemu_register_reset(nic_reset, 0, s); + qemu_register_reset(nic_reset, s); nic_reset(s); =20 s->mmio_index =3D cpu_register_io_memory(0, dp8393x_read, dp8393x_wr= ite, s); diff --git a/hw/eccmemctl.c b/hw/eccmemctl.c index aa4218d..07f5ef7 100644 --- a/hw/eccmemctl.c +++ b/hw/eccmemctl.c @@ -334,7 +334,7 @@ void * ecc_init(target_phys_addr_t base, qemu_irq irq= , uint32_t version) ecc_io_memory); } register_savevm("ECC", base, 3, ecc_save, ecc_load, s); - qemu_register_reset(ecc_reset, 0, s); + qemu_register_reset(ecc_reset, s); ecc_reset(s); return s; } diff --git a/hw/eepro100.c b/hw/eepro100.c index fcb091c..1689a3a 100644 --- a/hw/eepro100.c +++ b/hw/eepro100.c @@ -1771,7 +1771,7 @@ static void nic_init(PCIDevice *pci_dev, uint32_t d= evice) =20 qemu_format_nic_info_str(s->vc, s->macaddr); =20 - qemu_register_reset(nic_reset, 0, s); + qemu_register_reset(nic_reset, s); =20 register_savevm(s->vc->model, -1, 3, nic_save, nic_load, s); } diff --git a/hw/es1370.c b/hw/es1370.c index 12f2ace..6589547 100644 --- a/hw/es1370.c +++ b/hw/es1370.c @@ -1055,7 +1055,7 @@ int es1370_init (PCIBus *bus) =20 pci_register_io_region (&d->dev, 0, 256, PCI_ADDRESS_SPACE_IO, es137= 0_map); register_savevm ("es1370", 0, 2, es1370_save, es1370_load, s); - qemu_register_reset (es1370_on_reset, 0, s); + qemu_register_reset (es1370_on_reset, s); =20 AUD_register_card ("es1370", &s->card); es1370_reset (s); diff --git a/hw/escc.c b/hw/escc.c index 3d982b5..53808e5 100644 --- a/hw/escc.c +++ b/hw/escc.c @@ -758,7 +758,7 @@ int escc_init(target_phys_addr_t base, qemu_irq irqA,= qemu_irq irqB, register_savevm("escc", base, 2, escc_save, escc_load, s); else register_savevm("escc", -1, 2, escc_save, escc_load, s); - qemu_register_reset(escc_reset, 0, s); + qemu_register_reset(escc_reset, s); escc_reset(s); return escc_io_memory; } @@ -932,6 +932,6 @@ void slavio_serial_ms_kbd_init(target_phys_addr_t bas= e, qemu_irq irq, "QEMU Sun Mouse"); qemu_add_kbd_event_handler(sunkbd_event, &s->chn[1]); register_savevm("slavio_serial_mouse", base, 2, escc_save, escc_load= , s); - qemu_register_reset(escc_reset, 0, s); + qemu_register_reset(escc_reset, s); escc_reset(s); } diff --git a/hw/esp.c b/hw/esp.c index 6ac8c35..302e897 100644 --- a/hw/esp.c +++ b/hw/esp.c @@ -682,7 +682,7 @@ static void esp_init1(SysBusDevice *dev) esp_reset(s); =20 register_savevm("esp", -1, 3, esp_save, esp_load, s); - qemu_register_reset(esp_reset, 0, s); + qemu_register_reset(esp_reset, s); =20 qdev_init_irq_sink(&dev->qdev, parent_esp_reset, 1); =20 diff --git a/hw/etraxfs.c b/hw/etraxfs.c index f82e1cd..f043c19 100644 --- a/hw/etraxfs.c +++ b/hw/etraxfs.c @@ -64,7 +64,7 @@ void bareetraxfs_init (ram_addr_t ram_size, cpu_model =3D "crisv32"; } env =3D cpu_init(cpu_model); - qemu_register_reset(main_cpu_reset, 0, env); + qemu_register_reset(main_cpu_reset, env); =20 /* allocate RAM */ phys_ram =3D qemu_ram_alloc(ram_size); diff --git a/hw/etraxfs_timer.c b/hw/etraxfs_timer.c index 793c5eb..f1144ea 100644 --- a/hw/etraxfs_timer.c +++ b/hw/etraxfs_timer.c @@ -327,7 +327,7 @@ static void etraxfs_timer_init(SysBusDevice *dev) timer_regs =3D cpu_register_io_memory(0, timer_read, timer_write, t)= ; sysbus_init_mmio(dev, 0x5c, timer_regs); =20 - qemu_register_reset(etraxfs_timer_reset, 0, t); + qemu_register_reset(etraxfs_timer_reset, t); } =20 static void etraxfs_timer_register(void) diff --git a/hw/fdc.c b/hw/fdc.c index 4c6284c..f4a4be0 100644 --- a/hw/fdc.c +++ b/hw/fdc.c @@ -1883,7 +1883,7 @@ static fdctrl_t *fdctrl_init_common (qemu_irq irq, = int dma_chann, } fdctrl_external_reset(fdctrl); register_savevm("fdc", io_base, 2, fdc_save, fdc_load, fdctrl); - qemu_register_reset(fdctrl_external_reset, 0, fdctrl); + qemu_register_reset(fdctrl_external_reset, fdctrl); for (i =3D 0; i < MAX_FD; i++) { fd_revalidate(&fdctrl->drives[i]); } diff --git a/hw/fw_cfg.c b/hw/fw_cfg.c index 8ac0e9d..e605cda 100644 --- a/hw/fw_cfg.c +++ b/hw/fw_cfg.c @@ -281,7 +281,7 @@ void *fw_cfg_init(uint32_t ctl_port, uint32_t data_po= rt, fw_cfg_add_i16(s, FW_CFG_NB_CPUS, (uint16_t)smp_cpus); =20 register_savevm("fw_cfg", -1, 1, fw_cfg_save, fw_cfg_load, s); - qemu_register_reset(fw_cfg_reset, 0, s); + qemu_register_reset(fw_cfg_reset, s); fw_cfg_reset(s); =20 return s; diff --git a/hw/g364fb.c b/hw/g364fb.c index b9bb318..54c201c 100644 --- a/hw/g364fb.c +++ b/hw/g364fb.c @@ -598,7 +598,7 @@ int g364fb_mm_init(target_phys_addr_t vram_base, s->vram =3D qemu_get_ram_ptr(s->vram_offset); s->irq =3D irq; =20 - qemu_register_reset(g364fb_reset, 0, s); + qemu_register_reset(g364fb_reset, s); register_savevm("g364fb", 0, 1, g364fb_save, g364fb_load, s); g364fb_reset(s); =20 diff --git a/hw/grackle_pci.c b/hw/grackle_pci.c index 581d1c5..e48db92 100644 --- a/hw/grackle_pci.c +++ b/hw/grackle_pci.c @@ -177,7 +177,7 @@ PCIBus *pci_grackle_init(uint32_t base, qemu_irq *pic= ) d->config[0x27] =3D 0x85; #endif register_savevm("grackle", 0, 1, pci_grackle_save, pci_grackle_load,= d); - qemu_register_reset(pci_grackle_reset, 0, d); + qemu_register_reset(pci_grackle_reset, d); pci_grackle_reset(d); =20 return s->bus; diff --git a/hw/heathrow_pic.c b/hw/heathrow_pic.c index 38ebe99..9a67ec0 100644 --- a/hw/heathrow_pic.c +++ b/hw/heathrow_pic.c @@ -230,7 +230,7 @@ qemu_irq *heathrow_pic_init(int *pmem_index, =20 register_savevm("heathrow_pic", -1, 1, heathrow_pic_save, heathrow_pic_load, s); - qemu_register_reset(heathrow_pic_reset, 0, s); + qemu_register_reset(heathrow_pic_reset, s); heathrow_pic_reset(s); return qemu_allocate_irqs(heathrow_pic_set_irq, s, 64); } diff --git a/hw/hpet.c b/hw/hpet.c index 29db325..c7945ec 100644 --- a/hw/hpet.c +++ b/hw/hpet.c @@ -580,7 +580,7 @@ void hpet_init(qemu_irq *irq) { } hpet_reset(s); register_savevm("hpet", -1, 1, hpet_save, hpet_load, s); - qemu_register_reset(hpet_reset, 0, s); + qemu_register_reset(hpet_reset, s); /* HPET Area */ iomemtype =3D cpu_register_io_memory(0, hpet_ram_read, hpet_ram_write, s); diff --git a/hw/hw.h b/hw/hw.h index a3f5717..dd11f0a 100644 --- a/hw/hw.h +++ b/hw/hw.h @@ -258,7 +258,7 @@ void unregister_savevm(const char *idstr, void *opaqu= e); =20 typedef void QEMUResetHandler(void *opaque); =20 -void qemu_register_reset(QEMUResetHandler *func, int order, void *opaque= ); +void qemu_register_reset(QEMUResetHandler *func, void *opaque); =20 /* handler to set the boot_device for a specific type of QEMUMachine */ /* return 0 if success */ diff --git a/hw/i8254.c b/hw/i8254.c index acdd234..44e4531 100644 --- a/hw/i8254.c +++ b/hw/i8254.c @@ -497,7 +497,7 @@ PITState *pit_init(int base, qemu_irq irq) =20 register_savevm("i8254", base, 1, pit_save, pit_load, pit); =20 - qemu_register_reset(pit_reset, 0, pit); + qemu_register_reset(pit_reset, pit); register_ioport_write(base, 4, 1, pit_ioport_write, pit); register_ioport_read(base, 3, 1, pit_ioport_read, pit); =20 diff --git a/hw/i8259.c b/hw/i8259.c index 40f8bee..adabd2b 100644 --- a/hw/i8259.c +++ b/hw/i8259.c @@ -508,7 +508,7 @@ static void pic_init1(int io_addr, int elcr_addr, Pic= State *s) register_ioport_read(elcr_addr, 1, 1, elcr_ioport_read, s); } register_savevm("i8259", io_addr, 1, pic_save, pic_load, s); - qemu_register_reset(pic_reset, 0, s); + qemu_register_reset(pic_reset, s); } =20 void pic_info(Monitor *mon) diff --git a/hw/ide.c b/hw/ide.c index f8da7c9..2412b87 100644 --- a/hw/ide.c +++ b/hw/ide.c @@ -3330,7 +3330,7 @@ void pci_cmd646_ide_init(PCIBus *bus, BlockDriverSt= ate **hd_table, ide_init2(&d->ide_if[2], hd_table[2], hd_table[3], irq[1]); =20 register_savevm("ide", 0, 2, pci_ide_save, pci_ide_load, d); - qemu_register_reset(cmd646_reset, 0, d); + qemu_register_reset(cmd646_reset, d); cmd646_reset(d); } =20 @@ -3373,7 +3373,7 @@ void pci_piix3_ide_init(PCIBus *bus, BlockDriverSta= te **hd_table, int devfn, pci_config_set_class(pci_conf, PCI_CLASS_STORAGE_IDE); pci_conf[PCI_HEADER_TYPE] =3D PCI_HEADER_TYPE_NORMAL; // header_type= =20 - qemu_register_reset(piix3_reset, 0, d); + qemu_register_reset(piix3_reset, d); piix3_reset(d); =20 pci_register_io_region((PCIDevice *)d, 4, 0x10, @@ -3413,7 +3413,7 @@ void pci_piix4_ide_init(PCIBus *bus, BlockDriverSta= te **hd_table, int devfn, pci_config_set_class(pci_conf, PCI_CLASS_STORAGE_IDE); pci_conf[PCI_HEADER_TYPE] =3D PCI_HEADER_TYPE_NORMAL; // header_type= =20 - qemu_register_reset(piix3_reset, 0, d); + qemu_register_reset(piix3_reset, d); piix3_reset(d); =20 pci_register_io_region((PCIDevice *)d, 4, 0x10, @@ -3754,7 +3754,7 @@ int pmac_ide_init (BlockDriverState **hd_table, qem= u_irq irq, pmac_ide_memory =3D cpu_register_io_memory(0, pmac_ide_read, pmac_ide_write, d); register_savevm("ide", 0, 1, pmac_ide_save, pmac_ide_load, d); - qemu_register_reset(pmac_ide_reset, 0, d); + qemu_register_reset(pmac_ide_reset, d); pmac_ide_reset(d); =20 return pmac_ide_memory; diff --git a/hw/ioapic.c b/hw/ioapic.c index 83ac25e..317c2c2 100644 --- a/hw/ioapic.c +++ b/hw/ioapic.c @@ -255,7 +255,7 @@ IOAPICState *ioapic_init(void) cpu_register_physical_memory(0xfec00000, 0x1000, io_memory); =20 register_savevm("ioapic", 0, 1, ioapic_save, ioapic_load, s); - qemu_register_reset(ioapic_reset, 0, s); + qemu_register_reset(ioapic_reset, s); =20 return s; } diff --git a/hw/iommu.c b/hw/iommu.c index ae0c56d..d52acd7 100644 --- a/hw/iommu.c +++ b/hw/iommu.c @@ -380,7 +380,7 @@ void *iommu_init(target_phys_addr_t addr, uint32_t ve= rsion, qemu_irq irq) cpu_register_physical_memory(addr, IOMMU_NREGS * 4, iommu_io_memory)= ; =20 register_savevm("iommu", addr, 2, iommu_save, iommu_load, s); - qemu_register_reset(iommu_reset, 0, s); + qemu_register_reset(iommu_reset, s); iommu_reset(s); return s; } diff --git a/hw/lm832x.c b/hw/lm832x.c index 74eeca2..decde55 100644 --- a/hw/lm832x.c +++ b/hw/lm832x.c @@ -501,7 +501,7 @@ static void lm8323_init(i2c_slave *i2c) =20 lm_kbd_reset(s); =20 - qemu_register_reset((void *) lm_kbd_reset, 0, s); + qemu_register_reset((void *) lm_kbd_reset, s); register_savevm("LM8323", -1, 0, lm_kbd_save, lm_kbd_load, s); } =20 diff --git a/hw/m48t59.c b/hw/m48t59.c index 4804443..c6829be 100644 --- a/hw/m48t59.c +++ b/hw/m48t59.c @@ -641,7 +641,7 @@ m48t59_t *m48t59_init (qemu_irq IRQ, target_phys_addr= _t mem_base, } qemu_get_timedate(&s->alarm, 0); =20 - qemu_register_reset(m48t59_reset, 0, s); + qemu_register_reset(m48t59_reset, s); save_base =3D mem_base ? mem_base : io_base; register_savevm("m48t59", save_base, 1, m48t59_save, m48t59_load, s)= ; =20 diff --git a/hw/mac_dbdma.c b/hw/mac_dbdma.c index 75a9f17..a94cd09 100644 --- a/hw/mac_dbdma.c +++ b/hw/mac_dbdma.c @@ -839,7 +839,7 @@ void* DBDMA_init (int *dbdma_mem_index) =20 *dbdma_mem_index =3D cpu_register_io_memory(0, dbdma_read, dbdma_wri= te, s); register_savevm("dbdma", -1, 1, dbdma_save, dbdma_load, s); - qemu_register_reset(dbdma_reset, 0, s); + qemu_register_reset(dbdma_reset, s); dbdma_reset(s); =20 dbdma_bh =3D qemu_bh_new(DBDMA_run_bh, s); diff --git a/hw/mac_nvram.c b/hw/mac_nvram.c index 1a1ca0d..36648d1 100644 --- a/hw/mac_nvram.c +++ b/hw/mac_nvram.c @@ -142,7 +142,7 @@ MacIONVRAMState *macio_nvram_init (int *mem_index, ta= rget_phys_addr_t size, *mem_index =3D s->mem_index; register_savevm("macio_nvram", -1, 1, macio_nvram_save, macio_nvram_= load, s); - qemu_register_reset(macio_nvram_reset, 0, s); + qemu_register_reset(macio_nvram_reset, s); macio_nvram_reset(s); =20 return s; diff --git a/hw/mips_jazz.c b/hw/mips_jazz.c index e496c28..bf1621e 100644 --- a/hw/mips_jazz.c +++ b/hw/mips_jazz.c @@ -146,7 +146,7 @@ void mips_jazz_init (ram_addr_t ram_size, fprintf(stderr, "Unable to find CPU definition\n"); exit(1); } - qemu_register_reset(main_cpu_reset, 0, env); + qemu_register_reset(main_cpu_reset, env); =20 /* allocate RAM */ ram_offset =3D qemu_ram_alloc(ram_size); diff --git a/hw/mips_malta.c b/hw/mips_malta.c index a300808..ea417cf 100644 --- a/hw/mips_malta.c +++ b/hw/mips_malta.c @@ -447,7 +447,7 @@ static MaltaFPGAState *malta_fpga_init(target_phys_ad= dr_t base, qemu_irq uart_ir s->uart =3D serial_mm_init(base + 0x900, 3, uart_irq, 230400, uart_c= hr, 1); =20 malta_fpga_reset(s); - qemu_register_reset(malta_fpga_reset, 0, s); + qemu_register_reset(malta_fpga_reset, s); =20 return s; } @@ -792,7 +792,7 @@ void mips_malta_init (ram_addr_t ram_size, fprintf(stderr, "Unable to find CPU definition\n"); exit(1); } - qemu_register_reset(main_cpu_reset, 0, env); + qemu_register_reset(main_cpu_reset, env); =20 /* allocate RAM */ if (ram_size > (256 << 20)) { diff --git a/hw/mips_mipssim.c b/hw/mips_mipssim.c index 1117db2..e4414b4 100644 --- a/hw/mips_mipssim.c +++ b/hw/mips_mipssim.c @@ -126,7 +126,7 @@ mips_mipssim_init (ram_addr_t ram_size, fprintf(stderr, "Unable to find CPU definition\n"); exit(1); } - qemu_register_reset(main_cpu_reset, 0, env); + qemu_register_reset(main_cpu_reset, env); =20 /* Allocate RAM. */ ram_offset =3D qemu_ram_alloc(ram_size); diff --git a/hw/mips_r4k.c b/hw/mips_r4k.c index ba8c7f6..6892060 100644 --- a/hw/mips_r4k.c +++ b/hw/mips_r4k.c @@ -171,7 +171,7 @@ void mips_r4k_init (ram_addr_t ram_size, fprintf(stderr, "Unable to find CPU definition\n"); exit(1); } - qemu_register_reset(main_cpu_reset, 0, env); + qemu_register_reset(main_cpu_reset, env); =20 /* allocate RAM */ if (ram_size > (256 << 20)) { diff --git a/hw/musicpal.c b/hw/musicpal.c index 1e0aff5..d4724dd 100644 --- a/hw/musicpal.c +++ b/hw/musicpal.c @@ -441,7 +441,7 @@ static i2c_interface *musicpal_audio_init(qemu_irq ir= q) musicpal_audio_writefn, s); cpu_register_physical_memory(MP_AUDIO_BASE, MP_AUDIO_SIZE, iomemtype= ); =20 - qemu_register_reset(musicpal_audio_reset, 0, s); + qemu_register_reset(musicpal_audio_reset, s); =20 return i2c; } @@ -1046,7 +1046,7 @@ static void mv88w8618_pic_init(SysBusDevice *dev) mv88w8618_pic_writefn, s); sysbus_init_mmio(dev, MP_PIC_SIZE, iomemtype); =20 - qemu_register_reset(mv88w8618_pic_reset, 0, s); + qemu_register_reset(mv88w8618_pic_reset, s); } =20 /* PIT register offsets */ diff --git a/hw/nseries.c b/hw/nseries.c index b412aa0..c219bfe 100644 --- a/hw/nseries.c +++ b/hw/nseries.c @@ -1329,7 +1329,7 @@ static void n8x0_init(ram_addr_t ram_size, const ch= ar *boot_device, binfo->initrd_filename =3D initrd_filename; arm_load_kernel(s->cpu->env, binfo); =20 - qemu_register_reset(n8x0_boot_init, 0, s); + qemu_register_reset(n8x0_boot_init, s); n8x0_boot_init(s); } =20 diff --git a/hw/omap1.c b/hw/omap1.c index 4a479b4..e6e0b3e 100644 --- a/hw/omap1.c +++ b/hw/omap1.c @@ -4797,7 +4797,7 @@ struct omap_mpu_state_s *omap310_mpu_init(unsigned = long sdram_size, omap_setup_dsp_mapping(omap15xx_dsp_mm); omap_setup_mpui_io(s); =20 - qemu_register_reset(omap1_mpu_reset, 0, s); + qemu_register_reset(omap1_mpu_reset, s); =20 return s; } diff --git a/hw/omap2.c b/hw/omap2.c index 6fccca4..8aaa9c9 100644 --- a/hw/omap2.c +++ b/hw/omap2.c @@ -4868,7 +4868,7 @@ struct omap_mpu_state_s *omap2420_mpu_init(unsigned= long sdram_size, * GPMC registers 6800a000 6800afff */ =20 - qemu_register_reset(omap2_mpu_reset, 0, s); + qemu_register_reset(omap2_mpu_reset, s); =20 return s; } diff --git a/hw/openpic.c b/hw/openpic.c index 51c8ad8..561c609 100644 --- a/hw/openpic.c +++ b/hw/openpic.c @@ -1249,7 +1249,7 @@ qemu_irq *openpic_init (PCIBus *bus, int *pmem_inde= x, int nb_cpus, opp->need_swap =3D 1; =20 register_savevm("openpic", 0, 2, openpic_save, openpic_load, opp); - qemu_register_reset(openpic_reset, 0, opp); + qemu_register_reset(openpic_reset, opp); =20 opp->irq_raise =3D openpic_irq_raise; opp->reset =3D openpic_reset; @@ -1709,7 +1709,7 @@ qemu_irq *mpic_init (target_phys_addr_t base, int n= b_cpus, mpp->reset =3D mpic_reset; =20 register_savevm("mpic", 0, 2, openpic_save, openpic_load, mpp); - qemu_register_reset(mpic_reset, 0, mpp); + qemu_register_reset(mpic_reset, mpp); mpp->reset(mpp); =20 return qemu_allocate_irqs(openpic_set_irq, mpp, mpp->max_irq); diff --git a/hw/parallel.c b/hw/parallel.c index f66e5eb..dd2eeda 100644 --- a/hw/parallel.c +++ b/hw/parallel.c @@ -448,7 +448,7 @@ ParallelState *parallel_init(int base, qemu_irq irq, = CharDriverState *chr) s->irq =3D irq; s->chr =3D chr; parallel_reset(s); - qemu_register_reset(parallel_reset, 0, s); + qemu_register_reset(parallel_reset, s); =20 if (qemu_chr_ioctl(chr, CHR_IOCTL_PP_READ_STATUS, &dummy) =3D=3D 0) = { s->hw_driver =3D 1; @@ -541,7 +541,7 @@ ParallelState *parallel_mm_init(target_phys_addr_t ba= se, int it_shift, qemu_irq s->chr =3D chr; s->it_shift =3D it_shift; parallel_reset(s); - qemu_register_reset(parallel_reset, 0, s); + qemu_register_reset(parallel_reset, s); =20 io_sw =3D cpu_register_io_memory(0, parallel_mm_read_sw, parallel_mm= _write_sw, s); cpu_register_physical_memory(base, 8 << it_shift, io_sw); diff --git a/hw/pc.c b/hw/pc.c index 66cc780..9071a47 100644 --- a/hw/pc.c +++ b/hw/pc.c @@ -81,7 +81,7 @@ static void option_rom_setup_reset(target_phys_addr_t a= ddr, unsigned size) cpu_physical_memory_read(addr, rrd->data, size); rrd->addr =3D addr; rrd->size =3D size; - qemu_register_reset(option_rom_reset, 0, rrd); + qemu_register_reset(option_rom_reset, rrd); } =20 static void ioport80_write(void *opaque, uint32_t addr, uint32_t data) @@ -875,7 +875,7 @@ static void pc_init1(ram_addr_t ram_size, /* XXX: enable it in all cases */ env->cpuid_features |=3D CPUID_APIC; } - qemu_register_reset(main_cpu_reset, 0, env); + qemu_register_reset(main_cpu_reset, env); if (pci_enabled) { apic_init(env); } diff --git a/hw/pckbd.c b/hw/pckbd.c index 3ef3594..dd52651 100644 --- a/hw/pckbd.c +++ b/hw/pckbd.c @@ -381,7 +381,7 @@ void i8042_init(qemu_irq kbd_irq, qemu_irq mouse_irq,= uint32_t io_base) #ifdef TARGET_I386 vmmouse_init(s->mouse); #endif - qemu_register_reset(kbd_reset, 0, s); + qemu_register_reset(kbd_reset, s); } =20 /* Memory mapped interface */ @@ -438,5 +438,5 @@ void i8042_mm_init(qemu_irq kbd_irq, qemu_irq mouse_i= rq, #ifdef TARGET_I386 vmmouse_init(s->mouse); #endif - qemu_register_reset(kbd_reset, 0, s); + qemu_register_reset(kbd_reset, s); } diff --git a/hw/pl181.c b/hw/pl181.c index 2ba7f28..277607c 100644 --- a/hw/pl181.c +++ b/hw/pl181.c @@ -458,7 +458,7 @@ static void pl181_init(SysBusDevice *dev) sysbus_init_irq(dev, &s->irq[1]); bd =3D qdev_init_bdrv(&dev->qdev, IF_SD); s->card =3D sd_init(bd, 0); - qemu_register_reset(pl181_reset, 0, s); + qemu_register_reset(pl181_reset, s); pl181_reset(s); /* ??? Save/restore. */ } diff --git a/hw/ppc405_boards.c b/hw/ppc405_boards.c index a8f9a28..1ace32e 100644 --- a/hw/ppc405_boards.c +++ b/hw/ppc405_boards.c @@ -165,7 +165,7 @@ static void ref405ep_fpga_init (uint32_t base) ref405ep_fpga_write, fpga); cpu_register_physical_memory(base, 0x00000100, fpga_memory); ref405ep_fpga_reset(fpga); - qemu_register_reset(&ref405ep_fpga_reset, 0, fpga); + qemu_register_reset(&ref405ep_fpga_reset, fpga); } =20 static void ref405ep_init (ram_addr_t ram_size, @@ -483,7 +483,7 @@ static void taihu_cpld_init (uint32_t base) taihu_cpld_write, cpld); cpu_register_physical_memory(base, 0x00000100, cpld_memory); taihu_cpld_reset(cpld); - qemu_register_reset(&taihu_cpld_reset, 0, cpld); + qemu_register_reset(&taihu_cpld_reset, cpld); } =20 static void taihu_405ep_init(ram_addr_t ram_size, diff --git a/hw/ppc405_uc.c b/hw/ppc405_uc.c index 8dc33c7..dfe1905 100644 --- a/hw/ppc405_uc.c +++ b/hw/ppc405_uc.c @@ -173,7 +173,7 @@ void ppc4xx_plb_init (CPUState *env) ppc_dcr_register(env, PLB0_BEAR, plb, &dcr_read_plb, &dcr_write_plb)= ; ppc_dcr_register(env, PLB0_BESR, plb, &dcr_read_plb, &dcr_write_plb)= ; ppc4xx_plb_reset(plb); - qemu_register_reset(ppc4xx_plb_reset, 0, plb); + qemu_register_reset(ppc4xx_plb_reset, plb); } =20 /***********************************************************************= ******/ @@ -249,7 +249,7 @@ void ppc4xx_pob_init (CPUState *env) ppc_dcr_register(env, POB0_BEAR, pob, &dcr_read_pob, &dcr_write_pob)= ; ppc_dcr_register(env, POB0_BESR0, pob, &dcr_read_pob, &dcr_write_pob= ); ppc_dcr_register(env, POB0_BESR1, pob, &dcr_read_pob, &dcr_write_pob= ); - qemu_register_reset(ppc4xx_pob_reset, 0, pob); + qemu_register_reset(ppc4xx_pob_reset, pob); ppc4xx_pob_reset(env); } =20 @@ -386,7 +386,7 @@ void ppc4xx_opba_init (CPUState *env, ppc4xx_mmio_t *= mmio, #endif ppc4xx_mmio_register(env, mmio, offset, 0x002, opba_read, opba_write, opba); - qemu_register_reset(ppc4xx_opba_reset, 0, opba); + qemu_register_reset(ppc4xx_opba_reset, opba); ppc4xx_opba_reset(opba); } =20 @@ -580,7 +580,7 @@ void ppc405_ebc_init (CPUState *env) =20 ebc =3D qemu_mallocz(sizeof(ppc4xx_ebc_t)); ebc_reset(ebc); - qemu_register_reset(&ebc_reset, 0, ebc); + qemu_register_reset(&ebc_reset, ebc); ppc_dcr_register(env, EBC0_CFGADDR, ebc, &dcr_read_ebc, &dcr_write_ebc); ppc_dcr_register(env, EBC0_CFGDATA, @@ -672,7 +672,7 @@ void ppc405_dma_init (CPUState *env, qemu_irq irqs[4]= ) dma =3D qemu_mallocz(sizeof(ppc405_dma_t)); memcpy(dma->irqs, irqs, 4 * sizeof(qemu_irq)); ppc405_dma_reset(dma); - qemu_register_reset(&ppc405_dma_reset, 0, dma); + qemu_register_reset(&ppc405_dma_reset, dma); ppc_dcr_register(env, DMA0_CR0, dma, &dcr_read_dma, &dcr_write_dma); ppc_dcr_register(env, DMA0_CT0, @@ -837,7 +837,7 @@ void ppc405_gpio_init (CPUState *env, ppc4xx_mmio_t *= mmio, gpio =3D qemu_mallocz(sizeof(ppc405_gpio_t)); gpio->base =3D offset; ppc405_gpio_reset(gpio); - qemu_register_reset(&ppc405_gpio_reset, 0, gpio); + qemu_register_reset(&ppc405_gpio_reset, gpio); #ifdef DEBUG_GPIO printf("%s: offset " PADDRX "\n", __func__, offset); #endif @@ -1028,7 +1028,7 @@ void ppc405_ocm_init (CPUState *env) ocm =3D qemu_mallocz(sizeof(ppc405_ocm_t)); ocm->offset =3D qemu_ram_alloc(4096); ocm_reset(ocm); - qemu_register_reset(&ocm_reset, 0, ocm); + qemu_register_reset(&ocm_reset, ocm); ppc_dcr_register(env, OCM0_ISARC, ocm, &dcr_read_ocm, &dcr_write_ocm); ppc_dcr_register(env, OCM0_ISACNTL, @@ -1280,7 +1280,7 @@ void ppc405_i2c_init (CPUState *env, ppc4xx_mmio_t = *mmio, #endif ppc4xx_mmio_register(env, mmio, offset, 0x011, i2c_read, i2c_write, i2c); - qemu_register_reset(ppc4xx_i2c_reset, 0, i2c); + qemu_register_reset(ppc4xx_i2c_reset, i2c); } =20 /***********************************************************************= ******/ @@ -1562,7 +1562,7 @@ void ppc4xx_gpt_init (CPUState *env, ppc4xx_mmio_t = *mmio, #endif ppc4xx_mmio_register(env, mmio, offset, 0x0D4, gpt_read, gpt_write, gpt); - qemu_register_reset(ppc4xx_gpt_reset, 0, gpt); + qemu_register_reset(ppc4xx_gpt_reset, gpt); } =20 /***********************************************************************= ******/ @@ -1787,7 +1787,7 @@ void ppc405_mal_init (CPUState *env, qemu_irq irqs[= 4]) for (i =3D 0; i < 4; i++) mal->irqs[i] =3D irqs[i]; ppc40x_mal_reset(mal); - qemu_register_reset(&ppc40x_mal_reset, 0, mal); + qemu_register_reset(&ppc40x_mal_reset, mal); ppc_dcr_register(env, MAL0_CFG, mal, &dcr_read_mal, &dcr_write_mal); ppc_dcr_register(env, MAL0_ESR, @@ -2171,7 +2171,7 @@ static void ppc405cr_cpc_init (CPUState *env, clk_s= etup_t clk_setup[7], ppc_dcr_register(env, PPC405CR_CPC0_SR, cpc, &dcr_read_crcpc, &dcr_write_crcpc); ppc405cr_clk_init(cpc); - qemu_register_reset(ppc405cr_cpc_reset, 0, cpc); + qemu_register_reset(ppc405cr_cpc_reset, cpc); ppc405cr_cpc_reset(cpc); } =20 @@ -2493,7 +2493,7 @@ static void ppc405ep_cpc_init (CPUState *env, clk_s= etup_t clk_setup[8], cpc->jtagid =3D 0x20267049; cpc->sysclk =3D sysclk; ppc405ep_cpc_reset(cpc); - qemu_register_reset(&ppc405ep_cpc_reset, 0, cpc); + qemu_register_reset(&ppc405ep_cpc_reset, cpc); ppc_dcr_register(env, PPC405EP_CPC0_BOOT, cpc, &dcr_read_epcpc, &dcr_write_epcpc); ppc_dcr_register(env, PPC405EP_CPC0_EPCTL, cpc, diff --git a/hw/ppc4xx_devs.c b/hw/ppc4xx_devs.c index 5c8d273..ddee8f6 100644 --- a/hw/ppc4xx_devs.c +++ b/hw/ppc4xx_devs.c @@ -60,7 +60,7 @@ CPUState *ppc4xx_init (const char *cpu_model, tb_clk->opaque =3D env; ppc_dcr_init(env, NULL, NULL); /* Register qemu callbacks */ - qemu_register_reset(&cpu_ppc_reset, 0, env); + qemu_register_reset(&cpu_ppc_reset, env); =20 return env; } @@ -498,7 +498,7 @@ qemu_irq *ppcuic_init (CPUState *env, qemu_irq *irqs,= ppc_dcr_register(env, dcr_base + i, uic, &dcr_read_uic, &dcr_write_uic); } - qemu_register_reset(ppcuic_reset, 0, uic); + qemu_register_reset(ppcuic_reset, uic); ppcuic_reset(uic); =20 return qemu_allocate_irqs(&ppcuic_set_irq, uic, UIC_MAX_IRQ); @@ -834,7 +834,7 @@ void ppc4xx_sdram_init (CPUState *env, qemu_irq irq, = int nbanks, memcpy(sdram->ram_sizes, ram_sizes, nbanks * sizeof(target_phys_addr_t)); sdram_reset(sdram); - qemu_register_reset(&sdram_reset, 0, sdram); + qemu_register_reset(&sdram_reset, sdram); ppc_dcr_register(env, SDRAM0_CFGADDR, sdram, &dcr_read_sdram, &dcr_write_sdram); ppc_dcr_register(env, SDRAM0_CFGDATA, diff --git a/hw/ppc4xx_pci.c b/hw/ppc4xx_pci.c index 45ab3be..c5c7d53 100644 --- a/hw/ppc4xx_pci.c +++ b/hw/ppc4xx_pci.c @@ -404,7 +404,7 @@ PCIBus *ppc4xx_pci_init(CPUState *env, qemu_irq pci_i= rqs[4], goto free; cpu_register_physical_memory(registers, PCI_REG_SIZE, index); =20 - qemu_register_reset(ppc4xx_pci_reset, 0, controller); + qemu_register_reset(ppc4xx_pci_reset, controller); =20 /* XXX load/save code not tested. */ register_savevm("ppc4xx_pci", ppc4xx_pci_id++, 1, diff --git a/hw/ppc_newworld.c b/hw/ppc_newworld.c index 88ad99d..ce35dd9 100644 --- a/hw/ppc_newworld.c +++ b/hw/ppc_newworld.c @@ -128,7 +128,7 @@ static void ppc_core99_init (ram_addr_t ram_size, #if 0 env->osi_call =3D vga_osi_call; #endif - qemu_register_reset(&cpu_ppc_reset, 0, env); + qemu_register_reset(&cpu_ppc_reset, env); envs[i] =3D env; } =20 diff --git a/hw/ppc_oldworld.c b/hw/ppc_oldworld.c index aeac6ae..377ed59 100644 --- a/hw/ppc_oldworld.c +++ b/hw/ppc_oldworld.c @@ -154,7 +154,7 @@ static void ppc_heathrow_init (ram_addr_t ram_size, /* Set time-base frequency to 16.6 Mhz */ cpu_ppc_tb_init(env, 16600000UL); env->osi_call =3D vga_osi_call; - qemu_register_reset(&cpu_ppc_reset, 0, env); + qemu_register_reset(&cpu_ppc_reset, env); envs[i] =3D env; } =20 diff --git a/hw/ppc_prep.c b/hw/ppc_prep.c index 4832107..ef499b3 100644 --- a/hw/ppc_prep.c +++ b/hw/ppc_prep.c @@ -573,7 +573,7 @@ static void ppc_prep_init (ram_addr_t ram_size, /* Set time-base frequency to 100 Mhz */ cpu_ppc_tb_init(env, 100UL * 1000UL * 1000UL); } - qemu_register_reset(&cpu_ppc_reset, 0, env); + qemu_register_reset(&cpu_ppc_reset, env); envs[i] =3D env; } =20 diff --git a/hw/ps2.c b/hw/ps2.c index b1352d0..fb77005 100644 --- a/hw/ps2.c +++ b/hw/ps2.c @@ -593,7 +593,7 @@ void *ps2_kbd_init(void (*update_irq)(void *, int), v= oid *update_arg) ps2_reset(&s->common); register_savevm("ps2kbd", 0, 3, ps2_kbd_save, ps2_kbd_load, s); qemu_add_kbd_event_handler(ps2_put_keycode, s); - qemu_register_reset(ps2_reset, 0, &s->common); + qemu_register_reset(ps2_reset, &s->common); return s; } =20 @@ -606,6 +606,6 @@ void *ps2_mouse_init(void (*update_irq)(void *, int),= void *update_arg) ps2_reset(&s->common); register_savevm("ps2mouse", 0, 2, ps2_mouse_save, ps2_mouse_load, s)= ; qemu_add_mouse_event_handler(ps2_mouse_event, s, 0, "QEMU PS/2 Mouse= "); - qemu_register_reset(ps2_reset, 0, &s->common); + qemu_register_reset(ps2_reset, &s->common); return s; } diff --git a/hw/rc4030.c b/hw/rc4030.c index a35360a..7fe84ff 100644 --- a/hw/rc4030.c +++ b/hw/rc4030.c @@ -810,7 +810,7 @@ void *rc4030_init(qemu_irq timer, qemu_irq jazz_bus, s->timer_irq =3D timer; s->jazz_bus_irq =3D jazz_bus; =20 - qemu_register_reset(rc4030_reset, 0, s); + qemu_register_reset(rc4030_reset, s); register_savevm("rc4030", 0, 2, rc4030_save, rc4030_load, s); rc4030_reset(s); =20 diff --git a/hw/sbi.c b/hw/sbi.c index a601a59..1993eec 100644 --- a/hw/sbi.c +++ b/hw/sbi.c @@ -155,7 +155,7 @@ void *sbi_init(target_phys_addr_t addr, qemu_irq **ir= q, qemu_irq **cpu_irq, cpu_register_physical_memory(addr, SBI_SIZE, sbi_io_memory); =20 register_savevm("sbi", addr, 1, sbi_save, sbi_load, s); - qemu_register_reset(sbi_reset, 0, s); + qemu_register_reset(sbi_reset, s); *irq =3D qemu_allocate_irqs(sbi_set_irq, s, 32); *cpu_irq =3D qemu_allocate_irqs(sbi_set_timer_irq_cpu, s, MAX_CPUS);= sbi_reset(s); diff --git a/hw/serial.c b/hw/serial.c index 71f545d..113829c 100644 --- a/hw/serial.c +++ b/hw/serial.c @@ -720,7 +720,7 @@ static void serial_init_core(SerialState *s, qemu_irq= irq, int baudbase, s->fifo_timeout_timer =3D qemu_new_timer(vm_clock, (QEMUTimerCB *) f= ifo_timeout_int, s); s->transmit_timer =3D qemu_new_timer(vm_clock, (QEMUTimerCB *) seria= l_xmit, s); =20 - qemu_register_reset(serial_reset, 0, s); + qemu_register_reset(serial_reset, s); serial_reset(s); =20 qemu_chr_add_handlers(s->chr, serial_can_receive1, serial_receive1, diff --git a/hw/slavio_intctl.c b/hw/slavio_intctl.c index e39e4f9..b688934 100644 --- a/hw/slavio_intctl.c +++ b/hw/slavio_intctl.c @@ -407,7 +407,7 @@ void *slavio_intctl_init(target_phys_addr_t addr, tar= get_phys_addr_t addrg, =20 register_savevm("slavio_intctl", addr, 1, slavio_intctl_save, slavio_intctl_load, s); - qemu_register_reset(slavio_intctl_reset, 0, s); + qemu_register_reset(slavio_intctl_reset, s); *irq =3D qemu_allocate_irqs(slavio_set_irq, s, 32); =20 *cpu_irq =3D qemu_allocate_irqs(slavio_set_timer_irq_cpu, s, MAX_CPU= S); diff --git a/hw/slavio_misc.c b/hw/slavio_misc.c index f335863..ecece54 100644 --- a/hw/slavio_misc.c +++ b/hw/slavio_misc.c @@ -501,7 +501,7 @@ void *slavio_misc_init(target_phys_addr_t base, targe= t_phys_addr_t power_base, =20 register_savevm("slavio_misc", base, 1, slavio_misc_save, slavio_mis= c_load, s); - qemu_register_reset(slavio_misc_reset, 0, s); + qemu_register_reset(slavio_misc_reset, s); slavio_misc_reset(s); =20 return s; diff --git a/hw/slavio_timer.c b/hw/slavio_timer.c index b5f9ec3..725b16d 100644 --- a/hw/slavio_timer.c +++ b/hw/slavio_timer.c @@ -391,7 +391,7 @@ static SLAVIO_TIMERState *slavio_timer_init(target_ph= ys_addr_t addr, slavio_timer_io_memory); register_savevm("slavio_timer", addr, 3, slavio_timer_save, slavio_timer_load, s); - qemu_register_reset(slavio_timer_reset, 0, s); + qemu_register_reset(slavio_timer_reset, s); slavio_timer_reset(s); =20 return s; diff --git a/hw/sparc32_dma.c b/hw/sparc32_dma.c index 6893b88..cab9af7 100644 --- a/hw/sparc32_dma.c +++ b/hw/sparc32_dma.c @@ -256,7 +256,7 @@ void *sparc32_dma_init(target_phys_addr_t daddr, qemu= _irq parent_irq, cpu_register_physical_memory(daddr, DMA_SIZE, dma_io_memory); =20 register_savevm("sparc32_dma", daddr, 2, dma_save, dma_load, s); - qemu_register_reset(dma_reset, 0, s); + qemu_register_reset(dma_reset, s); *dev_irq =3D qemu_allocate_irqs(dma_set_irq, s, 1); =20 *reset =3D &s->dev_reset; diff --git a/hw/sun4c_intctl.c b/hw/sun4c_intctl.c index 8978e48..1b55557 100644 --- a/hw/sun4c_intctl.c +++ b/hw/sun4c_intctl.c @@ -213,7 +213,7 @@ void *sun4c_intctl_init(target_phys_addr_t addr, qemu= _irq **irq, register_savevm("sun4c_intctl", addr, 1, sun4c_intctl_save, sun4c_intctl_load, s); =20 - qemu_register_reset(sun4c_intctl_reset, 0, s); + qemu_register_reset(sun4c_intctl_reset, s); *irq =3D qemu_allocate_irqs(sun4c_set_irq, s, 8); =20 sun4c_intctl_reset(s); diff --git a/hw/sun4m.c b/hw/sun4m.c index af9f871..a2e0231 100644 --- a/hw/sun4m.c +++ b/hw/sun4m.c @@ -418,9 +418,9 @@ static void sun4m_hw_init(const struct sun4m_hwdef *h= wdef, ram_addr_t RAM_size, cpu_sparc_set_id(env, i); envs[i] =3D env; if (i =3D=3D 0) { - qemu_register_reset(main_cpu_reset, 0, env); + qemu_register_reset(main_cpu_reset, env); } else { - qemu_register_reset(secondary_cpu_reset, 0, env); + qemu_register_reset(secondary_cpu_reset, env); env->halted =3D 1; } cpu_irqs[i] =3D qemu_allocate_irqs(cpu_set_irq, envs[i], MAX_PIL= S); @@ -1201,9 +1201,9 @@ static void sun4d_hw_init(const struct sun4d_hwdef = *hwdef, ram_addr_t RAM_size, cpu_sparc_set_id(env, i); envs[i] =3D env; if (i =3D=3D 0) { - qemu_register_reset(main_cpu_reset, 0, env); + qemu_register_reset(main_cpu_reset, env); } else { - qemu_register_reset(secondary_cpu_reset, 0, env); + qemu_register_reset(secondary_cpu_reset, env); env->halted =3D 1; } cpu_irqs[i] =3D qemu_allocate_irqs(cpu_set_irq, envs[i], MAX_PIL= S); @@ -1416,7 +1416,7 @@ static void sun4c_hw_init(const struct sun4c_hwdef = *hwdef, ram_addr_t RAM_size, =20 cpu_sparc_set_id(env, 0); =20 - qemu_register_reset(main_cpu_reset, 0, env); + qemu_register_reset(main_cpu_reset, env); cpu_irqs =3D qemu_allocate_irqs(cpu_set_irq, env, MAX_PILS); env->prom_addr =3D hwdef->slavio_base; =20 diff --git a/hw/sun4u.c b/hw/sun4u.c index f5bb732..08789bc 100644 --- a/hw/sun4u.c +++ b/hw/sun4u.c @@ -374,7 +374,7 @@ static void sun4uv_init(ram_addr_t RAM_size, reset_info =3D qemu_mallocz(sizeof(ResetData)); reset_info->env =3D env; reset_info->reset_addr =3D hwdef->prom_addr + 0x40ULL; - qemu_register_reset(main_cpu_reset, 0, reset_info); + qemu_register_reset(main_cpu_reset, reset_info); main_cpu_reset(reset_info); // Override warm reset address with cold start address env->pc =3D hwdef->prom_addr + 0x20ULL; diff --git a/hw/tcx.c b/hw/tcx.c index 450ff9d..99e65a0 100644 --- a/hw/tcx.c +++ b/hw/tcx.c @@ -560,7 +560,7 @@ void tcx_init(target_phys_addr_t addr, int vram_size,= int width, int height, dummy_memory); =20 register_savevm("tcx", addr, 4, tcx_save, tcx_load, s); - qemu_register_reset(tcx_reset, 0, s); + qemu_register_reset(tcx_reset, s); tcx_reset(s); qemu_console_resize(s->ds, width, height); } diff --git a/hw/tsc2005.c b/hw/tsc2005.c index 36d6b53..2e71b8e 100644 --- a/hw/tsc2005.c +++ b/hw/tsc2005.c @@ -548,7 +548,7 @@ void *tsc2005_init(qemu_irq pintdav) qemu_add_mouse_event_handler(tsc2005_touchscreen_event, s, 1, "QEMU TSC2005-driven Touchscreen"); =20 - qemu_register_reset((void *) tsc2005_reset, 0, s); + qemu_register_reset((void *) tsc2005_reset, s); register_savevm("tsc2005", -1, 0, tsc2005_save, tsc2005_load, s); =20 return s; diff --git a/hw/tsc210x.c b/hw/tsc210x.c index a5ab574..16874e0 100644 --- a/hw/tsc210x.c +++ b/hw/tsc210x.c @@ -1143,7 +1143,7 @@ uWireSlave *tsc2102_init(qemu_irq pint) =20 AUD_register_card(s->name, &s->card); =20 - qemu_register_reset((void *) tsc210x_reset, 0, s); + qemu_register_reset((void *) tsc210x_reset, s); register_savevm(s->name, -1, 0, tsc210x_save, tsc210x_load, s); =20 @@ -1194,7 +1194,7 @@ uWireSlave *tsc2301_init(qemu_irq penirq, qemu_irq = kbirq, qemu_irq dav) =20 AUD_register_card(s->name, &s->card); =20 - qemu_register_reset((void *) tsc210x_reset, 0, s); + qemu_register_reset((void *) tsc210x_reset, s); register_savevm(s->name, -1, 0, tsc210x_save, tsc210x_load, s); =20 return &s->chip; diff --git a/hw/unin_pci.c b/hw/unin_pci.c index a9ef217..45aebf5 100644 --- a/hw/unin_pci.c +++ b/hw/unin_pci.c @@ -266,7 +266,7 @@ PCIBus *pci_pmac_init(qemu_irq *pic) d->config[0x34] =3D 0x00; // capabilities_pointer #endif register_savevm("uninorth", 0, 1, pci_unin_save, pci_unin_load, d); - qemu_register_reset(pci_unin_reset, 0, d); + qemu_register_reset(pci_unin_reset, d); pci_unin_reset(d); =20 return s->bus; diff --git a/hw/usb-ohci.c b/hw/usb-ohci.c index 1cc1b62..09944d0 100644 --- a/hw/usb-ohci.c +++ b/hw/usb-ohci.c @@ -1695,7 +1695,7 @@ static void usb_ohci_init(OHCIState *ohci, int num_= ports, int devfn, } =20 ohci->async_td =3D 0; - qemu_register_reset(ohci_reset, 0, ohci); + qemu_register_reset(ohci_reset, ohci); ohci_reset(ohci); } =20 diff --git a/hw/vga.c b/hw/vga.c index 013ff10..d228c59 100644 --- a/hw/vga.c +++ b/hw/vga.c @@ -2306,7 +2306,7 @@ void vga_init(VGAState *s) { int vga_io_memory; =20 - qemu_register_reset(vga_reset, 0, s); + qemu_register_reset(vga_reset, s); register_savevm("vga", 0, 2, vga_save, vga_load, s); =20 register_ioport_write(0x3c0, 16, 1, vga_ioport_write, s); diff --git a/hw/virtio.c b/hw/virtio.c index 45a49fa..463d74b 100644 --- a/hw/virtio.c +++ b/hw/virtio.c @@ -636,8 +636,7 @@ VirtIODevice *virtio_common_init(const char *name, ui= nt16_t device_id, else vdev->config =3D NULL; =20 - qemu_register_reset(virtio_reset, 0, vdev); - + qemu_register_reset(virtio_reset, vdev); return vdev; } =20 diff --git a/kvm-all.c b/kvm-all.c index 1364982..0827ae2 100644 --- a/kvm-all.c +++ b/kvm-all.c @@ -186,7 +186,7 @@ int kvm_init_vcpu(CPUState *env) =20 ret =3D kvm_arch_init_vcpu(env); if (ret =3D=3D 0) { - qemu_register_reset(kvm_reset_vcpu, 0, env); + qemu_register_reset(kvm_reset_vcpu, env); ret =3D kvm_arch_put_registers(env); } err: diff --git a/vl.c b/vl.c index 8b38fd1..b798b81 100644 --- a/vl.c +++ b/vl.c @@ -3579,7 +3579,6 @@ void vm_start(void) typedef struct QEMUResetEntry { QEMUResetHandler *func; void *opaque; - int order; struct QEMUResetEntry *next; } QEMUResetEntry; =20 @@ -3635,18 +3634,16 @@ static void do_vm_stop(int reason) } } =20 -void qemu_register_reset(QEMUResetHandler *func, int order, void *opaque= ) +void qemu_register_reset(QEMUResetHandler *func, void *opaque) { QEMUResetEntry **pre, *re; =20 pre =3D &first_reset_entry; - while (*pre !=3D NULL && (*pre)->order >=3D order) { + while (*pre !=3D NULL) pre =3D &(*pre)->next; - } re =3D qemu_mallocz(sizeof(QEMUResetEntry)); re->func =3D func; re->opaque =3D opaque; - re->order =3D order; re->next =3D NULL; *pre =3D re; } --------------enig7F36BAA7B41300D3A7A242CC Content-Type: application/pgp-signature; name="signature.asc" Content-Description: OpenPGP digital signature Content-Disposition: attachment; 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