From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mailman by lists.gnu.org with tmda-scanned (Exim 4.43) id 1M9JoF-0007uE-85 for qemu-devel@nongnu.org; Wed, 27 May 2009 10:08:47 -0400 Received: from exim by lists.gnu.org with spam-scanned (Exim 4.43) id 1M9JoA-0007tu-LH for qemu-devel@nongnu.org; Wed, 27 May 2009 10:08:46 -0400 Received: from [199.232.76.173] (port=41043 helo=monty-python.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1M9JoA-0007tr-HS for qemu-devel@nongnu.org; Wed, 27 May 2009 10:08:42 -0400 Received: from e8.ny.us.ibm.com ([32.97.182.138]:38170) by monty-python.gnu.org with esmtps (TLS-1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.60) (envelope-from ) id 1M9Jo9-0007QM-JB for qemu-devel@nongnu.org; Wed, 27 May 2009 10:08:41 -0400 Received: from d01relay02.pok.ibm.com (d01relay02.pok.ibm.com [9.56.227.234]) by e8.ny.us.ibm.com (8.13.1/8.13.1) with ESMTP id n4RDwIwY019423 for ; Wed, 27 May 2009 09:58:18 -0400 Received: from d01av01.pok.ibm.com (d01av01.pok.ibm.com [9.56.224.215]) by d01relay02.pok.ibm.com (8.13.8/8.13.8/NCO v9.2) with ESMTP id n4RE8cfx131932 for ; Wed, 27 May 2009 10:08:38 -0400 Received: from d01av01.pok.ibm.com (loopback [127.0.0.1]) by d01av01.pok.ibm.com (8.12.11.20060308/8.13.3) with ESMTP id n4RE8b77025528 for ; Wed, 27 May 2009 10:08:37 -0400 Message-ID: <4A1D4961.1010903@us.ibm.com> Date: Wed, 27 May 2009 09:08:33 -0500 From: Anthony Liguori MIME-Version: 1.0 Subject: Re: [Qemu-devel] [PATCH 2/3] Add PCI memory region registration References: <1243157375-14329-1-git-send-email-avi@redhat.com> <1243157375-14329-3-git-send-email-avi@redhat.com> In-Reply-To: <1243157375-14329-3-git-send-email-avi@redhat.com> Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Avi Kivity Cc: qemu-devel@nongnu.org Avi Kivity wrote: > A registered PCI memory region will be automatically mapped and unmapped > as the associated BAR is manipulated. > > Signed-off-by: Avi Kivity > --- > hw/pci.c | 78 +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++- > hw/pci.h | 26 ++++++++++++++++++++ > 2 files changed, 103 insertions(+), 1 deletions(-) > > diff --git a/hw/pci.h b/hw/pci.h > index ff858a1..b27e8fd 100644 > --- a/hw/pci.h > +++ b/hw/pci.h > @@ -2,6 +2,7 @@ > #define QEMU_PCI_H > > #include "qemu-common.h" > +#include "sys-queue.h" > > /* PCI includes legacy ISA access. */ > #include "isa.h" > @@ -80,11 +81,21 @@ typedef int PCIUnregisterFunc(PCIDevice *pci_dev); > #define PCI_ADDRESS_SPACE_IO 0x01 > #define PCI_ADDRESS_SPACE_MEM_PREFETCH 0x08 > > +typedef struct PCIIORegionComponent { > + PhysicalMemoryRegion *pmr; > + target_phys_addr_t offset; > + target_phys_addr_t size; > + ram_addr_t ram_addr; > + ram_addr_t region_offset; > + LIST_ENTRY(PCIIORegionComponent) link; > +} PCIIORegionComponent; > + > typedef struct PCIIORegion { > uint32_t addr; /* current PCI mapping address. -1 means not mapped */ > uint32_t size; > uint8_t type; > PCIMapIORegionFunc *map_func; > + LIST_HEAD(pci_region_list, PCIIORegionComponent) components; > } PCIIORegion; > > #define PCI_ROM_SLOT 6 > @@ -171,6 +182,21 @@ void pci_register_io_region(PCIDevice *pci_dev, int region_num, > uint32_t size, int type, > PCIMapIORegionFunc *map_func); > > +PCIIORegionComponent *pci_register_physical_memory(PCIDevice *pci_dev, > + int region_num, > + target_phys_addr_t size, > + ram_addr_t ram_addr); > PCI devices should not care about physical memory. They should only care about IO regions. It ought to look something like: enum { PCI_REGION_IO, PCI_REGION_MEM, }; typedef struct PCIIOFunction { uint32_t (*read)(void *opaque, uint64_t offset, int size); void (*write)(void *opaque, uint64_t offset, int size, uint64_t value); } PCIIOFunction; pci_register_io_region(PCIDevice *pci_dev, int region_num, int region_type, int order, PCIIOFunction *io_func, void *opaque); The current PCI map API goes away. Devices don't have to know anything about that. Special handling for PIO/MMIO for PCI devices also go away. Devices can register PCI_REGION_IO regions and they'll be automatically mapped to MMIO for non-x86 architectures. This means a lot of current PCI devices can be built once instead of being built for each architecture. If you want, we can setup a temporary branch in qemu to stage the conversion. I'm willing to help do the conversion too. Regards, Anthony Liguori