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Date: Tue, 09 Jun 2009 12:23:21 +0200
From: Jan Kiszka <jan.kiszka@siemens.com>
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Subject: [Qemu-devel] Re: [PATCHv2] Add rtc reset function.
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To: Gleb Natapov <gleb@redhat.com>
Cc: qemu-devel@nongnu.org

Gleb Natapov wrote:
> On reset:
> Periodic Interrupt Enable (PIE) bit is cleared to zero
> Alarm Interrupt Enable (AIE) bit is cleared to zero
> Update ended Interrupt Flag (UF) bit is cleared to zero
> Interrupt Request status Flag (IRQF) bit is cleared to zero
> Periodic Interrupt Flag (PF) bit is cleared to zero
> Alarm Interrupt Flag (AF) bit is cleared to zero
> Square Wave output Enable (SQWE) zero
> 
> Signed-off-by: Gleb Natapov <gleb@redhat.com>
> diff --git a/hw/mc146818rtc.c b/hw/mc146818rtc.c
> index 888b85a..8c446e1 100644
> --- a/hw/mc146818rtc.c
> +++ b/hw/mc146818rtc.c
> @@ -57,6 +57,11 @@
>  #define REG_B_SQWE 0x08
>  #define REG_B_DM   0x04
>  
> +#define REG_C_UF   0x10
> +#define REG_C_IRQF 0x80
> +#define REG_C_PF   0x40
> +#define REG_C_AF   0x20
> +
>  struct RTCState {
>      uint8_t cmos_data[128];
>      uint8_t cmos_index;
> @@ -568,6 +573,21 @@ static int rtc_load_td(QEMUFile *f, void *opaque, int version_id)
>  }
>  #endif
>  
> +static void rtc_reset(void *opaque)
> +{
> +    RTCState *s = opaque;
> +
> +    s->cmos_data[RTC_REG_B] &= ~(REG_B_PIE | REG_B_AIE | REG_B_SQWE);
> +    s->cmos_data[RTC_REG_C] &= ~(REG_C_UF | REG_C_IRQF | REG_C_PF | REG_C_AF);
> +
> +    qemu_irq_lower(s->irq);
> +
> +#ifdef TARGET_I386
> +    if (rtc_td_hack)
> +	    s->irq_coalesced = 0;

Sorry, missed that on first run: Isn't it safer, clearer, more beautiful
to reset this unconditionally?

Jan