From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mailman by lists.gnu.org with tmda-scanned (Exim 4.43) id 1MGpN5-00021r-0o for qemu-devel@nongnu.org; Wed, 17 Jun 2009 03:15:47 -0400 Received: from exim by lists.gnu.org with spam-scanned (Exim 4.43) id 1MGpMz-0001wu-Ak for qemu-devel@nongnu.org; Wed, 17 Jun 2009 03:15:45 -0400 Received: from [199.232.76.173] (port=37922 helo=monty-python.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1MGpMz-0001wi-36 for qemu-devel@nongnu.org; Wed, 17 Jun 2009 03:15:41 -0400 Received: from mx20.gnu.org ([199.232.41.8]:16422) by monty-python.gnu.org with esmtps (TLS-1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.60) (envelope-from ) id 1MGpMy-000847-Mf for qemu-devel@nongnu.org; Wed, 17 Jun 2009 03:15:40 -0400 Received: from mx2.redhat.com ([66.187.237.31]) by mx20.gnu.org with esmtp (Exim 4.60) (envelope-from ) id 1MGpMy-0002Ct-1J for qemu-devel@nongnu.org; Wed, 17 Jun 2009 03:15:40 -0400 Message-ID: <4A38979B.4030701@redhat.com> Date: Wed, 17 Jun 2009 10:13:31 +0300 From: Avi Kivity MIME-Version: 1.0 Subject: Re: [Qemu-devel] [PATCH] sparc64: use pci_mem_base References: <200906170013.38327.paul@codesourcery.com> <200906170106.39575.paul@codesourcery.com> In-Reply-To: <200906170106.39575.paul@codesourcery.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Paul Brook Cc: qemu-devel@nongnu.org On 06/17/2009 03:06 AM, Paul Brook wrote: >> Like pci bus would handle that memory address mapping between >> devices and cpu? >> > > Yes. In fact individual devices generally shouldn't need to know about the > mappings at all. They should just provide a handler for accesses via a > particular BAR. > I have a patch series which may help with this, I just need to rebase it. -- Do not meddle in the internals of kernels, for they are subtle and quick to panic.