From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mailman by lists.gnu.org with tmda-scanned (Exim 4.43) id 1MMN89-0006Zk-8V for qemu-devel@nongnu.org; Thu, 02 Jul 2009 10:19:17 -0400 Received: from exim by lists.gnu.org with spam-scanned (Exim 4.43) id 1MMN84-0006Yc-NJ for qemu-devel@nongnu.org; Thu, 02 Jul 2009 10:19:16 -0400 Received: from [199.232.76.173] (port=37800 helo=monty-python.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1MMN84-0006YZ-KH for qemu-devel@nongnu.org; Thu, 02 Jul 2009 10:19:12 -0400 Received: from relay3.sgi.com ([192.48.156.57]:53927 helo=relay.sgi.com) by monty-python.gnu.org with esmtp (Exim 4.60) (envelope-from ) id 1MMN84-0000Yw-69 for qemu-devel@nongnu.org; Thu, 02 Jul 2009 10:19:12 -0400 Message-ID: <4A4CC1DD.8070101@sgi.com> Date: Thu, 02 Jul 2009 16:19:09 +0200 From: Jes Sorensen MIME-Version: 1.0 Content-Type: multipart/mixed; boundary="------------050906050303020000070307" Subject: [Qemu-devel] [PATCH] Seabios maxcpus support List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Kevin O'Connor Cc: qemu-devel This is a multi-part message in MIME format. --------------050906050303020000070307 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Hi Kevin, Here's the patch I mentioned for maxcpus support for Seabios. I believe there will be other things we need to add to Seabios that we have in the qemu-kvm tree already, including -numa support and support for external ACPI tables, so the QEMU_CFG split should help that too. Cheers, Jes --------------050906050303020000070307 Content-Type: text/x-patch; name="0003-qemu-maxcpus.patch" Content-Transfer-Encoding: 7bit Content-Disposition: attachment; filename="0003-qemu-maxcpus.patch" Introduce support for max_cpus and use it to generate MADT and SSDT tables. If nothing provided, default to 15, to make sure not to break certain legacy OSes. This is similar in functionality to what was pushed into QEMU/BOCHS. Signed-off-by: Jes Sorense --- src/acpi.c | 21 ++++++++++++++------- src/qemu-cfg.c | 8 ++++++++ src/qemu-cfg.h | 3 +++ 3 files changed, 25 insertions(+), 7 deletions(-) Index: seabios/src/acpi.c =================================================================== --- seabios.orig/src/acpi.c +++ seabios/src/acpi.c @@ -12,7 +12,7 @@ #include "biosvar.h" // GET_EBDA #include "pci_ids.h" // PCI_VENDOR_ID_INTEL #include "pci_regs.h" // PCI_INTERRUPT_LINE - +#include "qemu-cfg.h" /****************************************************/ /* ACPI tables init */ @@ -213,6 +213,11 @@ struct madt_intsrcovr { } PACKED; #include "acpi-dsdt.hex" +/* + * Maximum number of supported CPUs, including hot-plug. + */ +#define MAX_CPUS_DEFAULT 15 +u16 max_cpus; static inline u16 cpu_to_le16(u16 x) { @@ -245,8 +250,7 @@ acpi_build_processor_ssdt(u8 *ssdt) { u8 *ssdt_ptr = ssdt; int i, length; - int smp_cpus = CountCPUs; - int acpi_cpus = smp_cpus > 0xff ? 0xff : smp_cpus; + int acpi_cpus = max_cpus > 0xff ? 0xff : max_cpus; ssdt_ptr[9] = 0; // checksum; ssdt_ptr += sizeof(struct acpi_table_header); @@ -301,6 +305,10 @@ void acpi_bios_init(void) if (! CONFIG_ACPI) return; + max_cpus = qemu_cfg_get_max_cpus(); + if (!max_cpus) + max_cpus = MAX_CPUS_DEFAULT; + dprintf(3, "init ACPI tables\n"); // This code is hardcoded for PIIX4 Power Management device. @@ -348,11 +356,10 @@ void acpi_bios_init(void) ssdt = (void *)(addr); addr += acpi_build_processor_ssdt(ssdt); - int smp_cpus = CountCPUs; addr = ALIGN(addr, 8); madt_addr = addr; madt_size = sizeof(*madt) + - sizeof(struct madt_processor_apic) * smp_cpus + + sizeof(struct madt_processor_apic) * max_cpus + sizeof(struct madt_io_apic); madt = (void *)(addr); addr += madt_size; @@ -417,7 +424,7 @@ void acpi_bios_init(void) madt->local_apic_address = cpu_to_le32(BUILD_APIC_ADDR); madt->flags = cpu_to_le32(1); struct madt_processor_apic *apic = (void *)&madt[1]; - for(i=0;itype = APIC_PROCESSOR; apic->length = sizeof(*apic); apic->processor_id = i; @@ -428,7 +435,7 @@ void acpi_bios_init(void) struct madt_io_apic *io_apic = (void *)apic; io_apic->type = APIC_IO; io_apic->length = sizeof(*io_apic); - io_apic->io_apic_id = smp_cpus; + io_apic->io_apic_id = max_cpus; io_apic->address = cpu_to_le32(BUILD_IOAPIC_ADDR); io_apic->interrupt = cpu_to_le32(0); Index: seabios/src/qemu-cfg.c =================================================================== --- seabios.orig/src/qemu-cfg.c +++ seabios/src/qemu-cfg.c @@ -27,3 +27,11 @@ qemu_cfg_port_probe() return *(u32*)buf == *(u32*)sig; } +u16 qemu_cfg_get_max_cpus(void) +{ + u16 cnt; + + qemu_cfg_read((u8*)&cnt, QEMU_CFG_MAX_CPUS, sizeof(cnt)); + + return cnt; +} Index: seabios/src/qemu-cfg.h =================================================================== --- seabios.orig/src/qemu-cfg.h +++ seabios/src/qemu-cfg.h @@ -12,8 +12,11 @@ #define QEMU_CFG_SIGNATURE 0x00 #define QEMU_CFG_ID 0x01 #define QEMU_CFG_UUID 0x02 +#define QEMU_CFG_MAX_CPUS 0x0E void qemu_cfg_read(u8 *buf, u16 f, int len); int qemu_cfg_port_probe(); +u16 qemu_cfg_get_max_cpus(void); + #endif --------------050906050303020000070307--