From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mailman by lists.gnu.org with tmda-scanned (Exim 4.43) id 1MPFxh-00070t-B0 for qemu-devel@nongnu.org; Fri, 10 Jul 2009 09:16:25 -0400 Received: from exim by lists.gnu.org with spam-scanned (Exim 4.43) id 1MPFxc-0006vD-Ib for qemu-devel@nongnu.org; Fri, 10 Jul 2009 09:16:24 -0400 Received: from [199.232.76.173] (port=38261 helo=monty-python.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1MPFxc-0006ue-AO for qemu-devel@nongnu.org; Fri, 10 Jul 2009 09:16:20 -0400 Received: from mail-yx0-f188.google.com ([209.85.210.188]:62983) by monty-python.gnu.org with esmtp (Exim 4.60) (envelope-from ) id 1MPFxb-0006a0-4g for qemu-devel@nongnu.org; Fri, 10 Jul 2009 09:16:19 -0400 Received: by yxe26 with SMTP id 26so1383093yxe.4 for ; Fri, 10 Jul 2009 06:16:18 -0700 (PDT) Message-ID: <4A573F1F.6090407@codemonkey.ws> Date: Fri, 10 Jul 2009 08:16:15 -0500 From: Anthony Liguori MIME-Version: 1.0 Subject: Re: [Qemu-devel] [PATCH 6/6] use uint32_t for ioport port and value instead of int. References: <1246530731-14597-1-git-send-email-yamahata@valinux.co.jp> <1246530731-14597-7-git-send-email-yamahata@valinux.co.jp> <4A564003.5080707@codemonkey.ws> <20090710082121.GB5471@const.bordeaux.inria.fr> <20090710084508.GM12665%yamahata@valinux.co.jp> <20090710085434.GK5471@const.bordeaux.inria.fr> <4A573B3F.1010900@codemonkey.ws> <761AD132-EDCD-4A26-B89F-3F4906BA5335@adacore.com> In-Reply-To: <761AD132-EDCD-4A26-B89F-3F4906BA5335@adacore.com> Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Tristan Gingold Cc: Isaku Yamahata , Samuel Thibault , qemu-devel@nongnu.org Tristan Gingold wrote: > Yes. > > Port IO is done through usual memory access, but either the processor > or the north-bridge can recognize this > address and convert the memory access to a port access. After all PCI > cards knows about IO vs Memory. So would we actually model this in QEMU through cpu_in/out? Can PCI IO regions that are marked as PIO actually be > 16-bit in size? Regards, Anthony Liguori