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Date: Thu, 16 Jul 2009 13:30:44 +0300
From: Naphtali Sprei <nsprei@redhat.com>
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Subject: Re: [Qemu-devel] 2nd try: [PATCH] fix for bad macaddr of e1000 in
	Windows 2003 server with original Microsoft driver
References: <4A5DC91F.7010009@redhat.com>	<1247683862.3824.2.camel@slab.beaverton.ibm.com>
	<20090715211011.GK3056@shareable.org>
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To: Jamie Lokier <jamie@shareable.org>
Cc: qemu-devel@nongnu.org, Hollis Blanchard <hollisb@us.ibm.com>

Jamie Lokier wrote:
> On Wed, 2009-07-15 at 15:18 +0300, Naphtali Sprei wrote:
>> After comments from quintela@trasno.org and mst@redhat.com, here's the 
>> 2nd try:
>>
>> The sequence of reading from eeprom is "offset by one" moved because
>> of a false detection of a clock cycle after an eeprom reset. Keeping
>> the last clock value after a reset keeps it in sync.
> 
> Isn't it more likely that the real hardware resets the clock value to
> a fixed level - the polarity being the opposite of what QEMU currently
> does, so that there's no edge caused by the first write?
The eeprom reset I referred to is actually a reset of the internal state of (part of) the device emulation in qemu.
The software drives the clock bit (SK) and the reset shouldn't change it. 
> 
> -- Jamie
> 
> 
> 
>