Re: [Qemu-devel] Re: [PATCH] HPET fixes for reg writes

[Beth Kon <eak@us.ibm.com>]

Andriy Gapon wrote:
> on 24/07/2009 19:26 Beth Kon said the following:
>   
>> This patch addresses the problems found by Andriy Gapon: 
>>
>> - The code was incorrectly overwriting the high order 32 
>>   bits of the timer and hpet config registers. This didn't show up
>>   in testing because linux and windows use hpet in legacy mode,
>>   where the high order 32 bits (advertising available interrupts)
>>   of the timer config register are ignored, and the high order 32
>>   bits of the hpet config register are reserved and unused.
>>
>>
>> - The mask for level-triggered interrupts was off by a bit. (hpet
>>   doesn't currently support level-triggered interrupts).
>>
>> In addition, I removed some unused #defines, and corrected the ioapic
>> interrupt values advertised. I'd set this up early in hpet development
>> and never went back to correct it, and no bugs resulted since linux and
>> windows use hpet in legacy mode where available interrupts are ignored.
>>
>>     
>
> Beth,
>
> thanks a lot!
>
> And a comment: it seems that the code doesn't verify interrupt configured by
> software, it happily uses any interrupt even if it's not advertised in interrupt
> capabilities. I know, the software should not do that, but it happens :)
>   
Yes, that is absolutely a good suggestion. I will add a check for 
correctness in the event of future expansion of hpet emulation 
capabilities, but see below.
> Also, maybe it would be a good idea to keep support for some additional
> interrupts? E.g. irq 10, 11 or some such, or maybe something >= 16 for APIC mode
> (if possible at all). But I know that this needs some careful thinking to not
> interfere with other emulated devices.
>   
Your probing on this subject has made clear that this hpet 
implementation really supports only legacy mode, because there are no 
other interrupts available for non-legacy mode hpet timers.

QEMU currently supports only a single IOAPIC, with irqs 0-15 identity 
mapped on to it (with the exception of irq0->inti2 override), and no 
capability for IOAPIC interrupts above 15. And since the hpet 
implementation is currently edge-triggered, it can not share interrupt 
lines with PCI. This leaves no interrupts other than the legacy timer 
interrupts. I will submit another patch that will make this clear. I 
will reduce the number of available timers to 2 (the 2 legacy mode 
timers), and not advertise  any  IOAPIC interrupt capability.

This could all be changed with qemu enhancements of course, but at the 
moment, hpet legacy replacement mode appears to reasonably cover the 
requirements of linux and windows guests.