From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mailman by lists.gnu.org with tmda-scanned (Exim 4.43) id 1MaRRP-0005bi-WB for qemu-devel@nongnu.org; Mon, 10 Aug 2009 05:45:20 -0400 Received: from exim by lists.gnu.org with spam-scanned (Exim 4.43) id 1MaRRL-0005am-VW for qemu-devel@nongnu.org; Mon, 10 Aug 2009 05:45:19 -0400 Received: from [199.232.76.173] (port=53382 helo=monty-python.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1MaRRL-0005aj-Nh for qemu-devel@nongnu.org; Mon, 10 Aug 2009 05:45:15 -0400 Received: from mx2.redhat.com ([66.187.237.31]:38603) by monty-python.gnu.org with esmtp (Exim 4.60) (envelope-from ) id 1MaRRL-00071W-7m for qemu-devel@nongnu.org; Mon, 10 Aug 2009 05:45:15 -0400 Message-ID: <4A7FEC23.1050708@redhat.com> Date: Mon, 10 Aug 2009 11:45:07 +0200 From: Stefan Assmann MIME-Version: 1.0 Subject: Re: [Qemu-devel] [PATCH 1/2] Route PC irqs to ISA bus instead of i8259 directly References: <1249836296-13288-1-git-send-email-avi@redhat.com> <1249836296-13288-2-git-send-email-avi@redhat.com> <2202BB40-5CA5-462B-8A5A-A9657B370B6D@suse.de> In-Reply-To: <2202BB40-5CA5-462B-8A5A-A9657B370B6D@suse.de> Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Alexander Graf Cc: Olaf Dabrunz , Avi Kivity , "qemu-devel@nongnu.org" On 10.08.2009 11:04, Alexander Graf wrote: > > Am 09.08.2009 um 18:44 schrieb Avi Kivity : > >> A PC has its motherboard IRQ lines connected to both the PIC and IOAPIC. >> Currently, qemu routes IRQs to the PIC which then calls the IOAPIC, an >> incestuous arrangement. In order to clean this up, create a new ISA IRQ >> abstraction, and have devices raise ISA IRQs (which in turn raise the >> i8259 >> IRQs as usual). > > Is this really true? From my understanding the PIC in modern systems is > emulated through the IOAPIC, which is the reason we have legacy interrupts. While not sure how the hardware implementation is done in detail I can confirm that the IRQs indeed end up at both PIC and IO-APIC0 if the device is connected to the southbridge directly. If that's not the case for example a PCI bus connected via PCIe that sports it's own IO-APIC then IRQs are forwarded (over PCIe) from the IO-APIC to the southbridge (PIC). In any case, to come closer to the real hardware having an abstraction that receives IRQs from devices and delivers them to the appropriate interrupt controller(s) seems to be a valid step IMHO. Does qemu support multiple IO-APICs? I guess not so no need for boot interrupts. (If yes then there would be the question how close you really want to be to existing hardware.) Stefan -- Stefan Assmann | Red Hat GmbH Software Engineer | Otto-Hahn-Strasse 20, 85609 Dornach | HR: Amtsgericht Muenchen HRB 153243 | GF: Brendan Lane, Charlie Peters, sassmann at redhat.com | Michael Cunningham, Charles Cachera