[Qemu-devel] sparc sun4m changes

[Qemu-devel] sparc sun4m changes

[Robert Reif]

I just took a look at the sun4m interrupt controller and noticed
the recent changes.  There are at least 3 different interrupt
controllers used by sun4m: ss600mp with VME and MBUS
specific support, ss 10/20 with MBUS support and ss 4/5/lx
with slavio support.  This doesn't even address the java stations.

intbit_to_level in slavio_intctrl.c needs to be different for each
controller chip used.  There also needs to be a controller specific
interrupt mask used.

The NCR slavio chip is only used for single processor systems
(ss 4/5/lx).  It is a subset of the ss 10/20 which is a subset of the
ss600mp.  We really should address these differences.

Re: [Qemu-devel] sparc sun4m changes

[Robert Reif]

Robert Reif wrote:
> I just took a look at the sun4m interrupt controller and noticed
> the recent changes.  There are at least 3 different interrupt
> controllers used by sun4m: ss600mp with VME and MBUS
> specific support, ss 10/20 with MBUS support and ss 4/5/lx
> with slavio support.  This doesn't even address the java stations.
>
> intbit_to_level in slavio_intctrl.c needs to be different for each
> controller chip used.  There also needs to be a controller specific
> interrupt mask used.
>
> The NCR slavio chip is only used for single processor systems
> (ss 4/5/lx).  It is a subset of the ss 10/20 which is a subset of the
> ss600mp.  We really should address these differences.
>
I forgot to mention the ss 10/20 uses an STP 2014 SBus to EBus
Interface Controller.  I have a paper copy of the User's Guide.  I
can have it scanned to a pdf if necessary.

The ss600mp uses ASICs with no documentation other than
the sun4m System Architecture manual and SPARCsystem 600MP
VMEbus Implementation Guide on:
http://wikis.sun.com/display/FOSSdocs/Home.

Re: [Qemu-devel] sparc sun4m changes

[Blue Swirl]

On Mon, Aug 10, 2009 at 5:28 AM, Robert Reif<reif@earthlink.net> wrote:
> Robert Reif wrote:
>>
>> I just took a look at the sun4m interrupt controller and noticed
>> the recent changes.  There are at least 3 different interrupt
>> controllers used by sun4m: ss600mp with VME and MBUS
>> specific support, ss 10/20 with MBUS support and ss 4/5/lx
>> with slavio support.  This doesn't even address the java stations.
>>
>> intbit_to_level in slavio_intctrl.c needs to be different for each
>> controller chip used.  There also needs to be a controller specific
>> interrupt mask used.
>>
>> The NCR slavio chip is only used for single processor systems
>> (ss 4/5/lx).  It is a subset of the ss 10/20 which is a subset of the
>> ss600mp.  We really should address these differences.
>>
> I forgot to mention the ss 10/20 uses an STP 2014 SBus to EBus
> Interface Controller.  I have a paper copy of the User's Guide.  I
> can have it scanned to a pdf if necessary.

I didn't find EBus on SS 10/20 OF trees, what's it used for? More docs
would be nice, though.

> The ss600mp uses ASICs with no documentation other than
> the sun4m System Architecture manual and SPARCsystem 600MP
> VMEbus Implementation Guide on:
> http://wikis.sun.com/display/FOSSdocs/Home.
>

There has been no activity in a year, are all devices documented already?

Re: [Qemu-devel] sparc sun4m changes

[Robert Reif]

Blue Swirl wrote:
>> The ss600mp uses ASICs with no documentation other than
>> the sun4m System Architecture manual and SPARCsystem 600MP
>> VMEbus Implementation Guide on:
>> http://wikis.sun.com/display/FOSSdocs/Home.
>>
>>     
>
> There has been no activity in a year, are all devices documented already?
>
>   
STP2013 and STP2014 (ss 10/20) are not documented.  I bought an
STP2014 manual off ebay.

The ss600mp documentation is pretty high level and not real useful.

[Qemu-devel] Re: sparc sun4m changes

[Blue Swirl]

On Mon, Aug 10, 2009 at 4:57 AM, Robert Reif<reif@earthlink.net> wrote:
> I just took a look at the sun4m interrupt controller and noticed
> the recent changes.  There are at least 3 different interrupt
> controllers used by sun4m: ss600mp with VME and MBUS
> specific support, ss 10/20 with MBUS support and ss 4/5/lx
> with slavio support.  This doesn't even address the java stations.
>
> intbit_to_level in slavio_intctrl.c needs to be different for each
> controller chip used.  There also needs to be a controller specific
> interrupt mask used.
>
> The NCR slavio chip is only used for single processor systems
> (ss 4/5/lx).  It is a subset of the ss 10/20 which is a subset of the
> ss600mp.  We really should address these differences.

I think the differences should be supported with a "model" or
"version" property rather than the intbit table, which didn't fit the
qdev model well.