From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mailman by lists.gnu.org with tmda-scanned (Exim 4.43) id 1Me50m-0005kg-8f for qemu-devel@nongnu.org; Thu, 20 Aug 2009 06:36:52 -0400 Received: from exim by lists.gnu.org with spam-scanned (Exim 4.43) id 1Me50h-0005k5-KE for qemu-devel@nongnu.org; Thu, 20 Aug 2009 06:36:51 -0400 Received: from [199.232.76.173] (port=32803 helo=monty-python.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1Me50g-0005k2-MD for qemu-devel@nongnu.org; Thu, 20 Aug 2009 06:36:46 -0400 Received: from sg2ehsobe003.messaging.microsoft.com ([207.46.51.77]:6613 helo=SG2EHSOBE003.bigfish.com) by monty-python.gnu.org with esmtps (TLS-1.0:RSA_ARCFOUR_MD5:16) (Exim 4.60) (envelope-from ) id 1Me50g-0002GQ-0p for qemu-devel@nongnu.org; Thu, 20 Aug 2009 06:36:46 -0400 Message-ID: <4A8D2722.2000905@amd.com> Date: Thu, 20 Aug 2009 12:36:18 +0200 From: Andre Przywara MIME-Version: 1.0 Subject: Re: [Qemu-devel] [PATCH 2/3] push CPUID level to 4 to allow Intel multicore decoding References: <1250689362-11067-1-git-send-email-andre.przywara@amd.com> <1250689362-11067-3-git-send-email-andre.przywara@amd.com> <4A8D2037.4000002@redhat.com> In-Reply-To: <4A8D2037.4000002@redhat.com> Content-Type: text/plain; charset="ISO-8859-1"; format=flowed Content-Transfer-Encoding: 7bit List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Avi Kivity Cc: qemu-devel@nongnu.org Avi Kivity wrote: > On 08/19/2009 04:42 PM, Andre Przywara wrote: >> Intel CPUs store the number of cores in CPUID leaf 4. So push >> the maxleaf value to 4 to allow the guests access to this leaf. >> > > There's a slight compatibility risk here. If a guest has broken > handling for cpuid level 4, then upgrading qemu would cause it to behave > differently. > > I don't think that's an issue for this patch, just highlighting the need > for a systematic treatment of backward compatibility. If you have real headaches about it, I have two options: What about allowing level to be specified at -cpu command line? This would allow users to say -cpu qemu64,level=2 if they experience problems. The default would stay at level 4. The other option would be to push the level only to four if we use more than one thread or core. In my research it turned out that Intel pushed the level beyond 4 with Pentium4 Prescott (probably with the introduction of real dual core chips to differentiate threads and cores), so this is quite some time ago. So I doubt that there are serious issues out there. The only problem I can think of is that the advertised cache topology is somehow bogus and could confuse OSes. Regards, Andre. -- Andre Przywara AMD-Operating System Research Center (OSRC), Dresden, Germany Tel: +49 351 448 3567 12 ----to satisfy European Law for business letters: Advanced Micro Devices GmbH Karl-Hammerschmidt-Str. 34, 85609 Dornach b. Muenchen Geschaeftsfuehrer: Thomas M. McCoy; Giuliano Meroni Sitz: Dornach, Gemeinde Aschheim, Landkreis Muenchen Registergericht Muenchen, HRB Nr. 43632