From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mailman by lists.gnu.org with tmda-scanned (Exim 4.43) id 1MgZb9-00052H-MV for qemu-devel@nongnu.org; Thu, 27 Aug 2009 03:40:43 -0400 Received: from exim by lists.gnu.org with spam-scanned (Exim 4.43) id 1MgZb5-00051M-93 for qemu-devel@nongnu.org; Thu, 27 Aug 2009 03:40:43 -0400 Received: from [199.232.76.173] (port=38824 helo=monty-python.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1MgZb5-00051J-5U for qemu-devel@nongnu.org; Thu, 27 Aug 2009 03:40:39 -0400 Received: from mx20.gnu.org ([199.232.41.8]:17968) by monty-python.gnu.org with esmtps (TLS-1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.60) (envelope-from ) id 1MgZb4-0000tw-N0 for qemu-devel@nongnu.org; Thu, 27 Aug 2009 03:40:38 -0400 Received: from mx1.redhat.com ([209.132.183.28]) by mx20.gnu.org with esmtp (Exim 4.60) (envelope-from ) id 1MgZb3-0004U9-Sp for qemu-devel@nongnu.org; Thu, 27 Aug 2009 03:40:38 -0400 Received: from int-mx02.intmail.prod.int.phx2.redhat.com (int-mx02.intmail.prod.int.phx2.redhat.com [10.5.11.12]) by mx1.redhat.com (8.13.8/8.13.8) with ESMTP id n7R7eDa8022428 for ; Thu, 27 Aug 2009 03:40:26 -0400 Message-ID: <4A963856.2040301@redhat.com> Date: Thu, 27 Aug 2009 09:40:06 +0200 From: Gerd Hoffmann MIME-Version: 1.0 Subject: Re: [Qemu-devel] [PATCH 2/2] Route IOAPIC interrupts via ISA bus References: <1249836296-13288-1-git-send-email-avi@redhat.com> <1249836296-13288-3-git-send-email-avi@redhat.com> <4A955CB4.4080205@redhat.com> <4A955D6A.9060804@redhat.com> <4A95633E.7060703@redhat.com> <20090826190944.GD11762@redhat.com> In-Reply-To: <20090826190944.GD11762@redhat.com> Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Gleb Natapov Cc: Avi Kivity , qemu-devel@nongnu.org On 08/26/09 21:09, Gleb Natapov wrote: > On Wed, Aug 26, 2009 at 06:30:54PM +0200, Gerd Hoffmann wrote: >> Right now we have IRQs 5,10,11 for PCI. Having one more IRQ (so we >> have one for each link) would be useful IMHO. eight links + eight >> irqs would be even more useful. What needs to be done for that? >> > Current code uses piix3 irq router to route pci interrupts to pic _and_ > ioapic and piix3 irq router supports only 16 interrupts. That means? We could add four more PCI links which have IRQs routed through another IRQ router chip and link them to ioapic lines 17-23 that way? Or does it mean we must emulate a more recent chipset? cheers, Gerd