From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mailman by lists.gnu.org with tmda-scanned (Exim 4.43) id 1MnKRa-0002a4-KQ for qemu-devel@nongnu.org; Mon, 14 Sep 2009 18:54:46 -0400 Received: from exim by lists.gnu.org with spam-scanned (Exim 4.43) id 1MnKRW-0002YV-Rf for qemu-devel@nongnu.org; Mon, 14 Sep 2009 18:54:46 -0400 Received: from [199.232.76.173] (port=33668 helo=monty-python.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1MnKRW-0002YJ-M9 for qemu-devel@nongnu.org; Mon, 14 Sep 2009 18:54:42 -0400 Received: from mail-yw0-f203.google.com ([209.85.211.203]:44144) by monty-python.gnu.org with esmtp (Exim 4.60) (envelope-from ) id 1MnKRW-0002nF-Av for qemu-devel@nongnu.org; Mon, 14 Sep 2009 18:54:42 -0400 Received: by ywh41 with SMTP id 41so4737401ywh.19 for ; Mon, 14 Sep 2009 15:54:41 -0700 (PDT) Message-ID: <4AAEC9AC.6080309@codemonkey.ws> Date: Mon, 14 Sep 2009 17:54:36 -0500 From: Anthony Liguori MIME-Version: 1.0 References: <20090914154822.GA3745@redhat.com> <4AAE7A31.9080600@codemonkey.ws> <20090914173625.GA3859@redhat.com> In-Reply-To: <20090914173625.GA3859@redhat.com> Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Subject: [Qemu-devel] Re: pci: is reset incomplete? List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: "Michael S. Tsirkin" Cc: Carsten Otte , Gerd Hoffmann , kvm@vger.kernel.org, Rusty Russell , qemu-devel@nongnu.org, virtualization@lists.linux-foundation.org, Christian Borntraeger , Paul Brook , Avi Kivity Michael S. Tsirkin wrote: > On Mon, Sep 14, 2009 at 12:15:29PM -0500, Anthony Liguori wrote: > >> Michael S. Tsirkin wrote: >> >>> Hi! >>> pci bus reset does not seem to clear pci config registers, such as BAR >>> registers, or memory space enable, of the attached devices: it only >>> clears the interrupt state. >>> >>> This seems wrong, but easy to fix. >>> >>> >> I don't think most pci devices reset their config space in their reset >> callbacks. >> > > For things like BAR registers, they really must. > BARs should be registered via pci_register_bar so you should be able to centralize their reset. > class codes are read only registers. Your proposal might be correct for > some of these. But PCI registers that are reset, change as a result of > guest activity, and reset values are typically specified by guest spec. > So I don't think we should let users tweak these. > Well, I guess my general point was that it would be good to add more structure to how config space is initialized. I think a natural consequence of that is that it becomes easier to automatically fix the values on reset. Regards, Anthony Liguori