From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mailman by lists.gnu.org with tmda-scanned (Exim 4.43) id 1MsNqn-0006Qp-MI for qemu-devel@nongnu.org; Mon, 28 Sep 2009 17:33:41 -0400 Received: from exim by lists.gnu.org with spam-scanned (Exim 4.43) id 1MsNqj-0006On-6x for qemu-devel@nongnu.org; Mon, 28 Sep 2009 17:33:41 -0400 Received: from [199.232.76.173] (port=54828 helo=monty-python.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1MsNqi-0006Oj-U6 for qemu-devel@nongnu.org; Mon, 28 Sep 2009 17:33:36 -0400 Received: from moutng.kundenserver.de ([212.227.126.188]:58259) by monty-python.gnu.org with esmtp (Exim 4.60) (envelope-from ) id 1MsNqi-0004qy-CE for qemu-devel@nongnu.org; Mon, 28 Sep 2009 17:33:36 -0400 Message-ID: <4AC12BAE.5030206@mail.berlios.de> Date: Mon, 28 Sep 2009 23:33:34 +0200 From: Stefan Weil MIME-Version: 1.0 Subject: Re: [Qemu-devel] [PATCH] tcg, tci: Add TCG and interpreter for bytecode (virtual machine) References: <4AC0E93A.6010605@mail.berlios.de> <1254156621-28559-1-git-send-email-weil@mail.berlios.de> In-Reply-To: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Blue Swirl , QEMU Developers Blue Swirl schrieb: > On Mon, Sep 28, 2009 at 7:50 PM, Stefan Weil wrote: > >> This is an initial and highly experimental version of >> a new code generator which does not create native code >> (so it will not depend on the host running qemu when it >> is finished). It creates bytecode which is interpreted. >> >> The current version can run the bios code, a simple >> hello world and the linux-user testcode for the >> i386 and x86_64 targets on x86_64 hosts. >> >> Some additional information is in tcg/bytecode/README >> which is part of the patch. >> >> Please send patches / enhancements based on my latest >> version from git://repo.or.cz/qemu/ar7.git. >> > > Nice. When the interpreter works, it should be unconditional for > targets that are not supported by TCG. > > >> +QEMU can create native code for some hosts (arm, hppa, i386, ppc, ppc64, >> +sparc, x86_64). For others, inoffical host support was written (s390). >> > > unofficial > > >> +static const int tcg_target_call_oarg_regs[2] = { >> + // TODO: ppc64 only uses one register. Why do others use two? >> > > To pass a 64 bit return value in two 32 bit registers? > > >> +static const char * const tcg_target_reg_names[TCG_TARGET_NB_REGS] = { >> > > >> +#if TCG_TARGET_NB_REGS == 16 || TCG_TARGET_NB_REGS == 32 >> > > >> + "r16", >> > > Table overflow. > > Thanks. Fixed in git://repo.or.cz/qemu/ar7.git