* [Qemu-devel] [PATCH 01/14] pcbios: add generated files to dot gitignore.
2009-09-30 10:18 [Qemu-devel] [PATCH 00/14] pcbios: support q35 chipset Isaku Yamahata
@ 2009-09-30 10:18 ` Isaku Yamahata
2009-09-30 10:18 ` [Qemu-devel] [PATCH 02/14] pcbios: fix makesym.perl Isaku Yamahata
` (13 subsequent siblings)
14 siblings, 0 replies; 20+ messages in thread
From: Isaku Yamahata @ 2009-09-30 10:18 UTC (permalink / raw)
To: qemu-devel, anthony; +Cc: yamahata
add dot gitignore to ignore generated files.
Signed-off-by: Isaku Yamahata <yamahata@valinux.co.jp>
---
.gitignore | 19 +++++++++++++++++++
1 files changed, 19 insertions(+), 0 deletions(-)
create mode 100644 .gitignore
diff --git a/.gitignore b/.gitignore
new file mode 100644
index 0000000..86e696c
--- /dev/null
+++ b/.gitignore
@@ -0,0 +1,19 @@
+BIOS-bochs-latest
+BIOS-bochs-legacy
+_rombios_.c
+_rombiosl_.c
+acpi-dsdt.aml
+acpi-dsdt.hex
+biossums
+config.mak
+rombios.s
+rombios.sym
+rombios.txt
+rombios16.bin
+rombios32.bin
+rombios32.o
+rombios32.out
+rombios32start.o
+rombiosl.s
+rombiosl.sym
+rombiosl.txt
--
1.6.0.2
^ permalink raw reply related [flat|nested] 20+ messages in thread* [Qemu-devel] [PATCH 02/14] pcbios: fix makesym.perl
2009-09-30 10:18 [Qemu-devel] [PATCH 00/14] pcbios: support q35 chipset Isaku Yamahata
2009-09-30 10:18 ` [Qemu-devel] [PATCH 01/14] pcbios: add generated files to dot gitignore Isaku Yamahata
@ 2009-09-30 10:18 ` Isaku Yamahata
2009-09-30 10:18 ` [Qemu-devel] [PATCH 03/14] pcbios: remove iasl output file when error Isaku Yamahata
` (12 subsequent siblings)
14 siblings, 0 replies; 20+ messages in thread
From: Isaku Yamahata @ 2009-09-30 10:18 UTC (permalink / raw)
To: qemu-devel, anthony; +Cc: yamahata
as86 symbols output doesn't always 7 colums.
[CNEI] may be appended depending on symbol type.
This patch makes the parser delete the type.
Signed-off-by: Isaku Yamahata <yamahata@valinux.co.jp>
---
Makefile | 4 ++--
makesym.perl | 1 +
2 files changed, 3 insertions(+), 2 deletions(-)
diff --git a/Makefile b/Makefile
index 5427abf..ddf30d3 100644
--- a/Makefile
+++ b/Makefile
@@ -54,7 +54,7 @@ dist-clean: clean
bios-clean:
$(RM) BIOS-bochs-*
-BIOS-bochs-legacy: rombios.c apmbios.S biossums rombios.h
+BIOS-bochs-legacy: rombios.c apmbios.S biossums rombios.h makesym.perl
$(CPP) $(BIOS_BUILD_DATE) -DLEGACY -P $< > _rombiosl_.c
$(BCC) -o rombiosl.s -C-c -D__i86__ -0 -S _rombiosl_.c
sed -e 's/^\.text//' -e 's/^\.data//' rombiosl.s > _rombiosl_.s
@@ -65,7 +65,7 @@ BIOS-bochs-legacy: rombios.c apmbios.S biossums rombios.h
$(RM) _rombiosl_.s
-rombios16.bin: rombios.c apmbios.S biossums rombios.h
+rombios16.bin: rombios.c apmbios.S biossums rombios.h makesym.perl
$(CPP) $(BIOS_BUILD_DATE) -P $< > _rombios_.c
$(BCC) -o rombios.s -C-c -D__i86__ -0 -S _rombios_.c
sed -e 's/^\.text//' -e 's/^\.data//' rombios.s > _rombios_.s
diff --git a/makesym.perl b/makesym.perl
index 0b6c94a..c220200 100755
--- a/makesym.perl
+++ b/makesym.perl
@@ -19,6 +19,7 @@ while (<STDIN>) {
$where = $WHERE_AFTER_SYM_TABLE;
}
if ($where == $WHERE_IN_SYM_TABLE) {
+ s/\b[CNEI]\b/ /eg;
@F = split (/\s+/);
($name[0], $junk, $addr[0], $junk, $name[1], $junk, $addr[1]) = @F;
foreach $col (0,1) {
--
1.6.0.2
^ permalink raw reply related [flat|nested] 20+ messages in thread* [Qemu-devel] [PATCH 03/14] pcbios: remove iasl output file when error.
2009-09-30 10:18 [Qemu-devel] [PATCH 00/14] pcbios: support q35 chipset Isaku Yamahata
2009-09-30 10:18 ` [Qemu-devel] [PATCH 01/14] pcbios: add generated files to dot gitignore Isaku Yamahata
2009-09-30 10:18 ` [Qemu-devel] [PATCH 02/14] pcbios: fix makesym.perl Isaku Yamahata
@ 2009-09-30 10:18 ` Isaku Yamahata
2009-09-30 10:18 ` [Qemu-devel] [PATCH 04/14] pcbios: make set_e820_range() full 64bit aware Isaku Yamahata
` (11 subsequent siblings)
14 siblings, 0 replies; 20+ messages in thread
From: Isaku Yamahata @ 2009-09-30 10:18 UTC (permalink / raw)
To: qemu-devel, anthony; +Cc: yamahata
Surprisingly iasl creates output file even when compilation error.
So typing make after an error will succeed.
This patch prevents it by removing the output file when error.
Signed-off-by: Isaku Yamahata <yamahata@valinux.co.jp>
---
Makefile | 2 +-
1 files changed, 1 insertions(+), 1 deletions(-)
diff --git a/Makefile b/Makefile
index ddf30d3..22599fa 100644
--- a/Makefile
+++ b/Makefile
@@ -88,7 +88,7 @@ rombios32.o: rombios32.c acpi-dsdt.hex
acpi-dsdt.hex: acpi-dsdt.dsl
$(CPP) -P $< > acpi-dsdt.dsl.i
- $(IASL) -tc -p $@ acpi-dsdt.dsl.i
+ $(IASL) -tc -p $@ acpi-dsdt.dsl.i || ($(RM) $@; exit 1)
$(RM) acpi-dsdt.dsl.i
sed -i -e's/^unsigned/const unsigned/' $@
--
1.6.0.2
^ permalink raw reply related [flat|nested] 20+ messages in thread* [Qemu-devel] [PATCH 04/14] pcbios: make set_e820_range() full 64bit aware.
2009-09-30 10:18 [Qemu-devel] [PATCH 00/14] pcbios: support q35 chipset Isaku Yamahata
` (2 preceding siblings ...)
2009-09-30 10:18 ` [Qemu-devel] [PATCH 03/14] pcbios: remove iasl output file when error Isaku Yamahata
@ 2009-09-30 10:18 ` Isaku Yamahata
2009-09-30 10:18 ` [Qemu-devel] [PATCH 05/14] pcbios: rombios32: make pci memory space assignment " Isaku Yamahata
` (10 subsequent siblings)
14 siblings, 0 replies; 20+ messages in thread
From: Isaku Yamahata @ 2009-09-30 10:18 UTC (permalink / raw)
To: qemu-devel, anthony; +Cc: yamahata
This patch makes e820 can return full 64bit value
instead of 40 bits.
This patch is preparation to make e820 cover PCIe MMCONFIG area
which is 64bit address in general.
Signed-off-by: Isaku Yamahata <yamahata@valinux.co.jp>
---
rombios.c | 24 ++++++++++++------------
1 files changed, 12 insertions(+), 12 deletions(-)
diff --git a/rombios.c b/rombios.c
index 560e6d5..6efd5d7 100644
--- a/rombios.c
+++ b/rombios.c
@@ -4466,21 +4466,21 @@ void set_e820_range(ES, DI, start, end, extra_start, extra_end, type)
Bit16u DI;
Bit32u start;
Bit32u end;
- Bit8u extra_start;
- Bit8u extra_end;
+ Bit32u extra_start;
+ Bit32u extra_end;
Bit16u type;
{
write_word(ES, DI, start);
write_word(ES, DI+2, start >> 16);
write_word(ES, DI+4, extra_start);
- write_word(ES, DI+6, 0x00);
+ write_word(ES, DI+6, extra_start >> 16);
end -= start;
extra_end -= extra_start;
write_word(ES, DI+8, end);
write_word(ES, DI+10, end >> 16);
write_word(ES, DI+12, extra_end);
- write_word(ES, DI+14, 0x0000);
+ write_word(ES, DI+14, extra_end >> 16);
write_word(ES, DI+16, type);
write_word(ES, DI+18, 0x0);
@@ -4494,7 +4494,7 @@ int15_function32(regs, ES, DS, FLAGS)
Bit32u extended_memory_size=0; // 64bits long
Bit32u extra_lowbits_memory_size=0;
Bit16u CX,DX;
- Bit8u extra_highbits_memory_size=0;
+ Bit32u extra_highbits_memory_size=0;
BX_DEBUG_INT15("int15 AX=%04x\n",regs.u.r16.ax);
@@ -4579,42 +4579,42 @@ ASM_END
{
case 0:
set_e820_range(ES, regs.u.r16.di,
- 0x0000000L, 0x0009f000L, 0, 0, 1);
+ 0x0000000L, 0x0009f000L, 0L, 0L, 1);
regs.u.r32.ebx = 1;
break;
case 1:
set_e820_range(ES, regs.u.r16.di,
- 0x0009f000L, 0x000a0000L, 0, 0, 2);
+ 0x0009f000L, 0x000a0000L, 0L, 0L, 2);
regs.u.r32.ebx = 2;
break;
case 2:
set_e820_range(ES, regs.u.r16.di,
- 0x000e8000L, 0x00100000L, 0, 0, 2);
+ 0x000e8000L, 0x00100000L, 0L, 0L, 2);
regs.u.r32.ebx = 3;
break;
case 3:
#if BX_ROMBIOS32
set_e820_range(ES, regs.u.r16.di,
0x00100000L,
- extended_memory_size - ACPI_DATA_SIZE ,0, 0, 1);
+ extended_memory_size - ACPI_DATA_SIZE ,0L, 0L, 1);
regs.u.r32.ebx = 4;
#else
set_e820_range(ES, regs.u.r16.di,
0x00100000L,
- extended_memory_size, 1);
+ extended_memory_size, 0L, 0L, 1);
regs.u.r32.ebx = 5;
#endif
break;
case 4:
set_e820_range(ES, regs.u.r16.di,
extended_memory_size - ACPI_DATA_SIZE,
- extended_memory_size ,0, 0, 3); // ACPI RAM
+ extended_memory_size ,0L, 0L, 3); // ACPI RAM
regs.u.r32.ebx = 5;
break;
case 5:
/* 256KB BIOS area at the end of 4 GB */
set_e820_range(ES, regs.u.r16.di,
- 0xfffc0000L, 0x00000000L ,0, 0, 2);
+ 0xfffc0000L, 0x00000000L ,0L, 0L, 2);
if (extra_highbits_memory_size || extra_lowbits_memory_size)
regs.u.r32.ebx = 6;
else
--
1.6.0.2
^ permalink raw reply related [flat|nested] 20+ messages in thread* [Qemu-devel] [PATCH 05/14] pcbios: rombios32: make pci memory space assignment 64bit aware.
2009-09-30 10:18 [Qemu-devel] [PATCH 00/14] pcbios: support q35 chipset Isaku Yamahata
` (3 preceding siblings ...)
2009-09-30 10:18 ` [Qemu-devel] [PATCH 04/14] pcbios: make set_e820_range() full 64bit aware Isaku Yamahata
@ 2009-09-30 10:18 ` Isaku Yamahata
2009-09-30 10:18 ` [Qemu-devel] [PATCH 06/14] pcbios: rombios32: make pci space assigner preferchable memory aware Isaku Yamahata
` (9 subsequent siblings)
14 siblings, 0 replies; 20+ messages in thread
From: Isaku Yamahata @ 2009-09-30 10:18 UTC (permalink / raw)
To: qemu-devel, anthony; +Cc: yamahata
make pci memory space assignment 64bit aware.
This patch is preparation for q35 chipset initialization which
has 64bit bar.
Signed-off-by: Isaku Yamahata <yamahata@valinux.co.jp>
---
rombios32.c | 10 ++++++++++
1 files changed, 10 insertions(+), 0 deletions(-)
diff --git a/rombios32.c b/rombios32.c
index 624f39f..19d3579 100644
--- a/rombios32.c
+++ b/rombios32.c
@@ -681,6 +681,9 @@ void smp_probe(void)
#define PCI_ADDRESS_SPACE_MEM 0x00
#define PCI_ADDRESS_SPACE_IO 0x01
+#define PCI_ADDRESS_SPACE_TYPE_MASK 0x06
+#define PCI_ADDRESS_SPACE_TYPE_32 0x00
+#define PCI_ADDRESS_SPACE_TYPE_64 0x04
#define PCI_ADDRESS_SPACE_MEM_PREFETCH 0x08
#define PCI_ROM_SLOT 6
@@ -1012,6 +1015,13 @@ static void pci_bios_init_device(PCIDevice *d)
pci_set_io_region_addr(d, i, *paddr);
*paddr += size;
}
+
+ /* 64bit bar */
+ if (!(val & PCI_ADDRESS_SPACE_IO) &&
+ (val & PCI_ADDRESS_SPACE_TYPE_MASK) ==
+ PCI_ADDRESS_SPACE_TYPE_64) {
+ i++;
+ }
}
break;
}
--
1.6.0.2
^ permalink raw reply related [flat|nested] 20+ messages in thread* [Qemu-devel] [PATCH 06/14] pcbios: rombios32: make pci space assigner preferchable memory aware.
2009-09-30 10:18 [Qemu-devel] [PATCH 00/14] pcbios: support q35 chipset Isaku Yamahata
` (4 preceding siblings ...)
2009-09-30 10:18 ` [Qemu-devel] [PATCH 05/14] pcbios: rombios32: make pci memory space assignment " Isaku Yamahata
@ 2009-09-30 10:18 ` Isaku Yamahata
2009-09-30 10:18 ` [Qemu-devel] [PATCH 07/14] pcbios: enable debug output for debug Isaku Yamahata
` (8 subsequent siblings)
14 siblings, 0 replies; 20+ messages in thread
From: Isaku Yamahata @ 2009-09-30 10:18 UTC (permalink / raw)
To: qemu-devel, anthony; +Cc: yamahata
make pci space assigner preferchable memory aware.
This is needed for PCI bridge support because memory space and
prefetchable memory space is filtered differently beased on
memory base/limit and prefetchable memory base/limit by pci bridge.
Signed-off-by: Isaku Yamahata <yamahata@valinux.co.jp>
---
rombios32.c | 16 +++++++++++++++-
1 files changed, 15 insertions(+), 1 deletions(-)
diff --git a/rombios32.c b/rombios32.c
index 19d3579..725f206 100644
--- a/rombios32.c
+++ b/rombios32.c
@@ -721,6 +721,8 @@ typedef struct PCIDevice {
static uint32_t pci_bios_io_addr;
static uint32_t pci_bios_mem_addr;
static uint32_t pci_bios_bigmem_addr;
+static uint32_t pci_bios_prefmem_addr;
+
/* host irqs corresponding to PCI irqs A-D */
static uint8_t pci_irqs[4] = { 10, 10, 11, 11 };
static PCIDevice i440_pcidev;
@@ -938,6 +940,11 @@ static void piix4_pm_enable(PCIDevice *d)
#endif
}
+static void pci_align_addr(uint32_t *paddr, uint32_t size)
+{
+ *paddr = (*paddr + size - 1) & ~(size - 1);
+}
+
static void pci_bios_init_device(PCIDevice *d)
{
int class;
@@ -1007,11 +1014,13 @@ static void pci_bios_init_device(PCIDevice *d)
size = (~(val & ~0xf)) + 1;
if (val & PCI_ADDRESS_SPACE_IO)
paddr = &pci_bios_io_addr;
+ else if (val & PCI_ADDRESS_SPACE_MEM_PREFETCH)
+ paddr = &pci_bios_prefmem_addr;
else if (size >= 0x04000000)
paddr = &pci_bios_bigmem_addr;
else
paddr = &pci_bios_mem_addr;
- *paddr = (*paddr + size - 1) & ~(size - 1);
+ pci_align_addr(paddr, size);
pci_set_io_region_addr(d, i, *paddr);
*paddr += size;
}
@@ -1072,6 +1081,11 @@ void pci_bios_init(void)
pci_bios_bigmem_addr = ram_size;
if (pci_bios_bigmem_addr < 0x90000000)
pci_bios_bigmem_addr = 0x90000000;
+ pci_bios_prefmem_addr = pci_bios_bigmem_addr + 0x08000000;
+ pci_align_addr(&pci_bios_prefmem_addr, 0x08000000);
+ if (pci_bios_prefmem_addr >= 0xe0000000) {
+ pci_bios_prefmem_addr = 0xf800000;
+ }
pci_for_each_device(pci_bios_init_bridges);
--
1.6.0.2
^ permalink raw reply related [flat|nested] 20+ messages in thread* [Qemu-devel] [PATCH 07/14] pcbios: enable debug output for debug.
2009-09-30 10:18 [Qemu-devel] [PATCH 00/14] pcbios: support q35 chipset Isaku Yamahata
` (5 preceding siblings ...)
2009-09-30 10:18 ` [Qemu-devel] [PATCH 06/14] pcbios: rombios32: make pci space assigner preferchable memory aware Isaku Yamahata
@ 2009-09-30 10:18 ` Isaku Yamahata
2009-09-30 10:18 ` [Qemu-devel] [PATCH 08/14] pcibos: initialize q35 chipset Isaku Yamahata
` (7 subsequent siblings)
14 siblings, 0 replies; 20+ messages in thread
From: Isaku Yamahata @ 2009-09-30 10:18 UTC (permalink / raw)
To: qemu-devel, anthony; +Cc: yamahata
enable debug output for debug.
doen't enable DEBUG_ATA because it causes qemu SEGV.
Signed-off-by: Isaku Yamahata <yamahata@valinux.co.jp>
---
rombios.c | 16 ++++++++--------
rombios.h | 2 +-
2 files changed, 9 insertions(+), 9 deletions(-)
diff --git a/rombios.c b/rombios.c
index 6efd5d7..fb4dce7 100644
--- a/rombios.c
+++ b/rombios.c
@@ -125,15 +125,15 @@
#include "rombios.h"
#define DEBUG_ATA 0
-#define DEBUG_INT13_HD 0
-#define DEBUG_INT13_CD 0
-#define DEBUG_INT13_ET 0
-#define DEBUG_INT13_FL 0
-#define DEBUG_INT15 0
+#define DEBUG_INT13_HD 1
+#define DEBUG_INT13_CD 1
+#define DEBUG_INT13_ET 1
+#define DEBUG_INT13_FL 1
+#define DEBUG_INT15 1
#define DEBUG_INT16 0
#define DEBUG_INT1A 0
-#define DEBUG_INT74 0
-#define DEBUG_APM 0
+#define DEBUG_INT74 1
+#define DEBUG_APM 1
#define BX_CPU 3
#define BX_USE_PS2_MOUSE 1
@@ -151,7 +151,7 @@
#define BX_MAX_ATA_DEVICES (BX_MAX_ATA_INTERFACES*2)
#define BX_VIRTUAL_PORTS 1 /* normal output to Bochs ports */
-#define BX_DEBUG_SERIAL 0 /* output to COM1 */
+#define BX_DEBUG_SERIAL 1 /* output to COM1 */
/* model byte 0xFC = AT */
#define SYS_MODEL_ID 0xFC
diff --git a/rombios.h b/rombios.h
index dbf3bd3..e1e3e6e 100644
--- a/rombios.h
+++ b/rombios.h
@@ -26,7 +26,7 @@
#else
# define BX_ROMBIOS32 0
#endif
-#define DEBUG_ROMBIOS 0
+#define DEBUG_ROMBIOS 1
#define PANIC_PORT 0x400
#define PANIC_PORT2 0x401
--
1.6.0.2
^ permalink raw reply related [flat|nested] 20+ messages in thread* [Qemu-devel] [PATCH 08/14] pcibos: initialize q35 chipset.
2009-09-30 10:18 [Qemu-devel] [PATCH 00/14] pcbios: support q35 chipset Isaku Yamahata
` (6 preceding siblings ...)
2009-09-30 10:18 ` [Qemu-devel] [PATCH 07/14] pcbios: enable debug output for debug Isaku Yamahata
@ 2009-09-30 10:18 ` Isaku Yamahata
2009-09-30 10:18 ` [Qemu-devel] [PATCH 09/14] pcbios: comment out PCI_FIXED_HOST_BRIDGE for gmch host pci bridge to undef Isaku Yamahata
` (6 subsequent siblings)
14 siblings, 0 replies; 20+ messages in thread
From: Isaku Yamahata @ 2009-09-30 10:18 UTC (permalink / raw)
To: qemu-devel, anthony; +Cc: yamahata
teach pcbios q35 chipset to initialize it properly.
Signed-off-by: Isaku Yamahata <yamahata@valinux.co.jp>
---
rombios32.c | 296 ++++++++++++++++++++++++++++++++++++++++++++++-------------
1 files changed, 233 insertions(+), 63 deletions(-)
diff --git a/rombios32.c b/rombios32.c
index 725f206..f7e906f 100644
--- a/rombios32.c
+++ b/rombios32.c
@@ -449,6 +449,7 @@ uint64_t ram_end;
unsigned long ebda_cur_addr;
#endif
int acpi_enabled;
+uint8_t acpi_enable, acpi_disable;
uint32_t pm_io_base, smb_io_base;
int pm_sci_int;
unsigned long bios_table_cur_addr;
@@ -710,6 +711,24 @@ void smp_probe(void)
#define PCI_DEVICE_ID_INTEL_82371AB 0x7111
#define PCI_DEVICE_ID_INTEL_82371AB_3 0x7113
+#define PCI_DEVICE_ID_INTEL_Q35_MCH 0x29c0
+#define Q35_HOST_BRIDGE_PAM0 0x90
+#define Q35_HOST_BRDIGE_SMRAM 0x9d
+
+#define PCI_DEVICE_ID_INTEL_ICH9_LPC 0x2918
+#define ICH9_LPC_PMBASE 0x40
+#define ICH9_PMBASE_SMI_EN 0x30
+#define ICH9_PMBASE_SMI_EN_APMC_EN (1 << 5)
+#define ICH9_LPC_ACPI_CTRL 0x44
+#define ICH9_LPC_ACPI_CTRL_ACPI_EN 0x80
+#define PCI_DEVICE_ID_INTEL_ICH9_SMBUS 0x2930
+#define ICH9_SMB_SMB_BASE 0x20
+#define ICH9_SMB_HOSTC 0x40
+#define ICH9_SMB_HOSTC_HST_EN 0x01
+
+#define ICH9_ACPI_ENABLE 0x2
+#define ICH9_ACPI_DISABLE 0x3
+
#define PCI_VENDOR_ID_IBM 0x1014
#define PCI_VENDOR_ID_APPLE 0x106b
@@ -726,6 +745,9 @@ static uint32_t pci_bios_prefmem_addr;
/* host irqs corresponding to PCI irqs A-D */
static uint8_t pci_irqs[4] = { 10, 10, 11, 11 };
static PCIDevice i440_pcidev;
+static int i440_found;
+static PCIDevice mch_pcidev;
+static int mch_found;
static void pci_config_writel(PCIDevice *d, uint32_t addr, uint32_t val)
{
@@ -815,7 +837,9 @@ static void find_bios_table_area(void)
return;
}
-static void bios_shadow_init(PCIDevice *d)
+/* i440 and mch have same pam0 register format with different offset */
+static void bios_shadow_init_common(PCIDevice *d, uint32_t pam0_addr,
+ PCIDevice *host_bridge, int *host_found)
{
int v;
@@ -824,43 +848,62 @@ static void bios_shadow_init(PCIDevice *d)
/* remap the BIOS to shadow RAM an keep it read/write while we
are writing tables */
- v = pci_config_readb(d, 0x59);
+ v = pci_config_readb(d, pam0_addr);
v &= 0xcf;
- pci_config_writeb(d, 0x59, v);
+ pci_config_writeb(d, pam0_addr, v);
memcpy((void *)BIOS_TMP_STORAGE, (void *)0x000f0000, 0x10000);
v |= 0x30;
- pci_config_writeb(d, 0x59, v);
+ pci_config_writeb(d, pam0_addr, v);
memcpy((void *)0x000f0000, (void *)BIOS_TMP_STORAGE, 0x10000);
- i440_pcidev = *d;
+ *host_bridge = *d;
+ *host_found = 1;
}
-static void bios_lock_shadow_ram(void)
+static void bios_lock_shadow_ram_common(PCIDevice *d, uint32_t pam0_addr)
{
- PCIDevice *d = &i440_pcidev;
int v;
wbinvd();
- v = pci_config_readb(d, 0x59);
+ v = pci_config_readb(d, pam0_addr);
v = (v & 0x0f) | (0x10);
- pci_config_writeb(d, 0x59, v);
+ pci_config_writeb(d, pam0_addr, v);
}
-static void pci_bios_init_bridges(PCIDevice *d)
+static void i440_bios_shadow_init(PCIDevice *d)
{
- uint16_t vendor_id, device_id;
+ bios_shadow_init_common(d, 0x59, &i440_pcidev, &i440_found);
+}
- vendor_id = pci_config_readw(d, PCI_VENDOR_ID);
- device_id = pci_config_readw(d, PCI_DEVICE_ID);
+static void i440_bios_lock_shadow_ram(PCIDevice *d)
+{
+ bios_lock_shadow_ram_common(d, 0x59);
+}
- if (vendor_id == PCI_VENDOR_ID_INTEL &&
- (device_id == PCI_DEVICE_ID_INTEL_82371SB_0 ||
- device_id == PCI_DEVICE_ID_INTEL_82371AB_0)) {
+static void mch_bios_shadow_init(PCIDevice *d)
+{
+ bios_shadow_init_common(d, Q35_HOST_BRIDGE_PAM0, &mch_pcidev, &mch_found);
+}
+
+static void mch_bios_lock_shadow_ram(PCIDevice *d)
+{
+ bios_lock_shadow_ram_common(d, Q35_HOST_BRIDGE_PAM0);
+}
+
+static void bios_lock_shadow_ram(void)
+{
+ if (i440_found)
+ i440_bios_lock_shadow_ram(&i440_pcidev);
+ if (mch_found)
+ mch_bios_lock_shadow_ram(&mch_pcidev);
+}
+
+/* piix and ich9 have same pirq a-d register format with different offset */
+static void pci_init_isa_bridge(PCIDevice *d, uint32_t addr, const char *name)
+{
int i, irq;
uint8_t elcr[2];
- /* PIIX3/PIIX4 PCI to ISA bridge */
-
elcr[0] = 0x00;
elcr[1] = 0x00;
for(i = 0; i < 4; i++) {
@@ -868,15 +911,37 @@ static void pci_bios_init_bridges(PCIDevice *d)
/* set to trigger level */
elcr[irq >> 3] |= (1 << (irq & 7));
/* activate irq remapping in PIIX */
- pci_config_writeb(d, 0x60 + i, irq);
+ pci_config_writeb(d, addr + i, irq);
}
outb(0x4d0, elcr[0]);
outb(0x4d1, elcr[1]);
- BX_INFO("PIIX3/PIIX4 init: elcr=%02x %02x\n",
- elcr[0], elcr[1]);
- } else if (vendor_id == PCI_VENDOR_ID_INTEL && device_id == PCI_DEVICE_ID_INTEL_82441) {
+ BX_INFO("%s init: elcr=%02x %02x\n", name, elcr[0], elcr[1]);
+}
+
+static void pci_bios_init_bridges(PCIDevice *d)
+{
+ uint16_t vendor_id, device_id;
+
+ vendor_id = pci_config_readw(d, PCI_VENDOR_ID);
+ device_id = pci_config_readw(d, PCI_DEVICE_ID);
+
+ if (vendor_id == PCI_VENDOR_ID_INTEL &&
+ (device_id == PCI_DEVICE_ID_INTEL_82371SB_0 ||
+ device_id == PCI_DEVICE_ID_INTEL_82371AB_0)) {
+ /* PIIX3/PIIX4 PCI to ISA bridge */
+ pci_init_isa_bridge(d, 0x60, "PIIX3/PIIX4");
+ } else if (vendor_id == PCI_VENDOR_ID_INTEL &&
+ device_id == PCI_DEVICE_ID_INTEL_ICH9_LPC) {
+ /* ICH9 LPC PCI to ISA bridge */
+ pci_init_isa_bridge(d, 0x60, "ICH9 LPC");
+ } else if (vendor_id == PCI_VENDOR_ID_INTEL &&
+ device_id == PCI_DEVICE_ID_INTEL_82441) {
/* i440 PCI bridge */
- bios_shadow_init(d);
+ i440_bios_shadow_init(d);
+ } else if (vendor_id == PCI_VENDOR_ID_INTEL &&
+ device_id == PCI_DEVICE_ID_INTEL_Q35_MCH) {
+ /* ich9 PCI host bridge */
+ mch_bios_shadow_init(d);
}
}
@@ -884,46 +949,64 @@ extern uint8_t smm_relocation_start, smm_relocation_end;
extern uint8_t smm_code_start, smm_code_end;
#ifdef BX_USE_SMM
-static void smm_init(PCIDevice *d)
+/* i440 and mch have same smram format with different offset
+ * and they have same 0xb2, 0xb3 io port
+ */
+static void smm_init(PCIDevice *d,
+ PCIDevice *host_bridge, uint32_t smram_addr,
+ void (*apmc_en)(PCIDevice *d))
{
- uint32_t value;
+ /* enable the SMM memory window */
+ pci_config_writeb(host_bridge, smram_addr, 0x02 | 0x48);
- /* check if SMM init is already done */
- value = pci_config_readl(d, 0x58);
- if ((value & (1 << 25)) == 0) {
+ /* save original memory content */
+ memcpy((void *)0xa8000, (void *)0x38000, 0x8000);
+
+ /* copy the SMM relocation code */
+ memcpy((void *)0x38000, &smm_relocation_start,
+ &smm_relocation_end - &smm_relocation_start);
- /* enable the SMM memory window */
- pci_config_writeb(&i440_pcidev, 0x72, 0x02 | 0x48);
+ /* enable SMI generation when writing to the APMC register */
+ apmc_en(d);
- /* save original memory content */
- memcpy((void *)0xa8000, (void *)0x38000, 0x8000);
+ /* init APM status port */
+ outb(0xb3, 0x01);
- /* copy the SMM relocation code */
- memcpy((void *)0x38000, &smm_relocation_start,
- &smm_relocation_end - &smm_relocation_start);
+ /* raise an SMI interrupt */
+ outb(0xb2, 0x00);
- /* enable SMI generation when writing to the APMC register */
- pci_config_writel(d, 0x58, value | (1 << 25));
+ /* wait until SMM code executed */
+ while (inb(0xb3) != 0x00);
- /* init APM status port */
- outb(0xb3, 0x01);
+ /* restore original memory content */
+ memcpy((void *)0x38000, (void *)0xa8000, 0x8000);
- /* raise an SMI interrupt */
- outb(0xb2, 0x00);
+ /* copy the SMM code */
+ memcpy((void *)0xa8000, &smm_code_start,
+ &smm_code_end - &smm_code_start);
+ wbinvd();
- /* wait until SMM code executed */
- while (inb(0xb3) != 0x00);
+ /* close the SMM memory window and enable normal SMM */
+ pci_config_writeb(host_bridge, smram_addr, 0x02 | 0x08);
+}
+#endif
- /* restore original memory content */
- memcpy((void *)0x38000, (void *)0xa8000, 0x8000);
+#ifdef BX_USE_SMM
+static void piix_apmc_enable(PCIDevice *d)
+{
+ uint32_t value;
+ value = pci_config_readl(d, 0x58);
+ pci_config_writel(d, 0x58, value | (1 << 25));
+}
- /* copy the SMM code */
- memcpy((void *)0xa8000, &smm_code_start,
- &smm_code_end - &smm_code_start);
- wbinvd();
+static void piix4_smm_init(PCIDevice *d)
+{
+ uint32_t value;
- /* close the SMM memory window and enable normal SMM */
- pci_config_writeb(&i440_pcidev, 0x72, 0x02 | 0x08);
+ /* check if SMM init is already done */
+ value = pci_config_readl(d, 0x58);
+ if ((value & (1 << 25)) == 0) {
+ smm_init(d, &i440_pcidev, 0x72, &piix_apmc_enable);
}
}
#endif
@@ -931,15 +1014,61 @@ static void smm_init(PCIDevice *d)
static void piix4_pm_enable(PCIDevice *d)
{
/* PIIX4 Power Management device (for ACPI) */
- pci_config_writel(d, 0x40, PM_IO_BASE | 1);
+ pci_config_writel(d, 0x40, pm_io_base | 1);
pci_config_writeb(d, 0x80, 0x01); /* enable PM io space */
- pci_config_writel(d, 0x90, SMB_IO_BASE | 1);
+ pci_config_writel(d, 0x90, smb_io_base | 1);
pci_config_writeb(d, 0xd2, 0x09); /* enable SMBus io space */
#ifdef BX_USE_SMM
- smm_init(d);
+ piix4_smm_init(d);
#endif
}
+#ifdef BX_USE_SMM
+static void ich9_apmc_enable(PCIDevice *d)
+{
+ uint32_t value;
+ value = inl(pm_io_base + ICH9_PMBASE_SMI_EN);
+ value |= ICH9_PMBASE_SMI_EN_APMC_EN;
+ outl(pm_io_base + ICH9_PMBASE_SMI_EN, value);
+}
+
+static void ich9_smm_init(PCIDevice *d)
+{
+ uint32_t value;
+
+ /* check if SMM init is already done */
+ value = inl(pm_io_base + ICH9_PMBASE_SMI_EN);
+ if ((value & ICH9_PMBASE_SMI_EN_APMC_EN) == 0) {
+ smm_init(d, &mch_pcidev,
+ Q35_HOST_BRDIGE_SMRAM, &ich9_apmc_enable);
+ }
+}
+#endif
+
+static void ich9_lpc_pm_enable(PCIDevice *d)
+{
+ uint8_t v;
+
+ pci_config_writel(d, ICH9_LPC_PMBASE, pm_io_base | 1);
+
+ v = pci_config_readb(d, ICH9_LPC_ACPI_CTRL);
+ v |= ICH9_LPC_ACPI_CTRL_ACPI_EN;
+ pci_config_writeb(d, ICH9_LPC_ACPI_CTRL, v);
+#ifdef BX_USE_SMM
+ ich9_smm_init(d);
+#endif
+}
+
+static void ich9_smbus_enable(PCIDevice *d)
+{
+ /* map smbus into io space */
+ pci_config_writel(d, ICH9_SMB_SMB_BASE,
+ smb_io_base | 1 /* 1 = io space */);
+
+ /* enable SMBus */
+ pci_config_writeb(d, ICH9_SMB_HOSTC, ICH9_SMB_HOSTC_HST_EN);
+}
+
static void pci_align_addr(uint32_t *paddr, uint32_t size)
{
*paddr = (*paddr + size - 1) & ~(size - 1);
@@ -1052,6 +1181,24 @@ static void pci_bios_init_device(PCIDevice *d)
pm_sci_int = pci_config_readb(d, PCI_INTERRUPT_LINE);
piix4_pm_enable(d);
acpi_enabled = 1;
+ acpi_enable = 0xf1;
+ acpi_disable = 0xf0;
+ } else if (vendor_id == PCI_VENDOR_ID_INTEL &&
+ device_id == PCI_DEVICE_ID_INTEL_ICH9_LPC) {
+ pm_io_base = PM_IO_BASE;
+
+ // acpi sci defaults to 9
+ pci_config_writeb(d, ICH9_LPC_ACPI_CTRL, 0 /* 000b = irq9 */);
+ pci_config_writeb(d, PCI_INTERRUPT_LINE, 9);
+ pm_sci_int = pci_config_readb(d, PCI_INTERRUPT_LINE);
+ ich9_lpc_pm_enable(d);
+ acpi_enabled = 1;
+ acpi_enable = ICH9_ACPI_ENABLE;
+ acpi_disable = ICH9_ACPI_DISABLE;
+ } else if (vendor_id == PCI_VENDOR_ID_INTEL &&
+ device_id == PCI_DEVICE_ID_INTEL_ICH9_SMBUS) {
+ smb_io_base = SMB_IO_BASE;
+ ich9_smbus_enable(d);
}
}
@@ -1789,19 +1936,28 @@ void acpi_bios_init(void)
fadt->model = 1;
fadt->reserved1 = 0;
fadt->sci_int = cpu_to_le16(pm_sci_int);
+ /* both piix4 and ich9 user io port 0xb2 = SMI_CMD_IO_ADDR, 0xb3 */
fadt->smi_cmd = cpu_to_le32(SMI_CMD_IO_ADDR);
- fadt->acpi_enable = 0xf1;
- fadt->acpi_disable = 0xf0;
+ fadt->acpi_enable = acpi_enable;
+ fadt->acpi_disable = acpi_disable;
+
+ /* both piix4 and ich9 have same offset from pm_io_base and length */
fadt->pm1a_evt_blk = cpu_to_le32(pm_io_base);
fadt->pm1a_cnt_blk = cpu_to_le32(pm_io_base + 0x04);
fadt->pm_tmr_blk = cpu_to_le32(pm_io_base + 0x08);
fadt->pm1_evt_len = 4;
fadt->pm1_cnt_len = 2;
fadt->pm_tmr_len = 4;
+
fadt->plvl2_lat = cpu_to_le16(0xfff); // C2 state not supported
fadt->plvl3_lat = cpu_to_le16(0xfff); // C3 state not supported
- fadt->gpe0_blk = cpu_to_le32(0xafe0);
- fadt->gpe0_blk_len = 4;
+ if (i440_found) {
+ fadt->gpe0_blk = cpu_to_le32(0xafe0);
+ fadt->gpe0_blk_len = 4;
+ } else if (mch_found) {
+ fadt->gpe0_blk = cpu_to_le32(pm_io_base + 0x20);
+ fadt->gpe0_blk_len = 0x10;
+ }
/* WBINVD + PROC_C1 + SLP_BUTTON + FIX_RTC */
fadt->flags = cpu_to_le32((1 << 0) | (1 << 2) | (1 << 5) | (1 << 6));
acpi_build_table_header((struct acpi_table_header *)fadt, "FACP",
@@ -2715,18 +2871,24 @@ static uint32_t find_resume_vector(void)
return 0;
}
-static void find_440fx(PCIDevice *d)
+static void find_hostbridge(PCIDevice *d)
{
uint16_t vendor_id, device_id;
vendor_id = pci_config_readw(d, PCI_VENDOR_ID);
device_id = pci_config_readw(d, PCI_DEVICE_ID);
- if (vendor_id == PCI_VENDOR_ID_INTEL && device_id == PCI_DEVICE_ID_INTEL_82441)
+ if (vendor_id == PCI_VENDOR_ID_INTEL && device_id == PCI_DEVICE_ID_INTEL_82441) {
i440_pcidev = *d;
+ i440_found = 1;
+ }
+ if (vendor_id == PCI_VENDOR_ID_INTEL && device_id == PCI_DEVICE_ID_INTEL_Q35_MCH) {
+ mch_pcidev = *d;
+ mch_found = 1;
+ }
}
-static void reinit_piix4_pm(PCIDevice *d)
+static void reinit_pm(PCIDevice *d)
{
uint16_t vendor_id, device_id;
@@ -2735,6 +2897,14 @@ static void reinit_piix4_pm(PCIDevice *d)
if (vendor_id == PCI_VENDOR_ID_INTEL && device_id == PCI_DEVICE_ID_INTEL_82371AB_3)
piix4_pm_enable(d);
+
+ if (vendor_id == PCI_VENDOR_ID_INTEL &&
+ device_id == PCI_DEVICE_ID_INTEL_ICH9_LPC)
+ ich9_lpc_pm_enable(d);
+
+ if (vendor_id == PCI_VENDOR_ID_INTEL &&
+ device_id == PCI_DEVICE_ID_INTEL_ICH9_SMBUS)
+ ich9_smbus_enable(d);
}
void rombios32_init(uint32_t *s3_resume_vector, uint8_t *shutdown_flag)
@@ -2764,14 +2934,14 @@ void rombios32_init(uint32_t *s3_resume_vector, uint8_t *shutdown_flag)
if (*shutdown_flag == 0xfe) {
/* redirect bios read access to RAM */
- pci_for_each_device(find_440fx);
+ pci_for_each_device(find_hostbridge);
bios_lock_shadow_ram(); /* bios is already copied */
*s3_resume_vector = find_resume_vector();
if (!*s3_resume_vector) {
BX_INFO("This is S3 resume but wakeup vector is NULL\n");
} else {
BX_INFO("S3 resume vector %p\n", *s3_resume_vector);
- pci_for_each_device(reinit_piix4_pm);
+ pci_for_each_device(reinit_pm);
}
return;
}
--
1.6.0.2
^ permalink raw reply related [flat|nested] 20+ messages in thread* [Qemu-devel] [PATCH 09/14] pcbios: comment out PCI_FIXED_HOST_BRIDGE for gmch host pci bridge to undef.
2009-09-30 10:18 [Qemu-devel] [PATCH 00/14] pcbios: support q35 chipset Isaku Yamahata
` (7 preceding siblings ...)
2009-09-30 10:18 ` [Qemu-devel] [PATCH 08/14] pcibos: initialize q35 chipset Isaku Yamahata
@ 2009-09-30 10:18 ` Isaku Yamahata
2009-09-30 10:18 ` [Qemu-devel] [PATCH 10/14] pcibos: add mcfg entry to ACPI table for q35 pcie Isaku Yamahata
` (5 subsequent siblings)
14 siblings, 0 replies; 20+ messages in thread
From: Isaku Yamahata @ 2009-09-30 10:18 UTC (permalink / raw)
To: qemu-devel, anthony; +Cc: yamahata
undef PCI_FIXED_HOST_BRIDGE to intialise only i440fx host pci bridge.
Now other PCI host bridge (in this case q35 gmch) is supported,
undef the constant.
Signed-off-by: Isaku Yamahata <yamahata@valinux.co.jp>
---
rombios.c | 4 +++-
1 files changed, 3 insertions(+), 1 deletions(-)
diff --git a/rombios.c b/rombios.c
index fb4dce7..2b94d76 100644
--- a/rombios.c
+++ b/rombios.c
@@ -202,7 +202,9 @@
// define this if you want to make PCIBIOS working on a specific bridge only
// undef enables PCIBIOS when at least one PCI device is found
// i440FX is emulated by Bochs and QEMU
-#define PCI_FIXED_HOST_BRIDGE 0x12378086 ;; i440FX PCI bridge
+//#define PCI_FIXED_HOST_BRIDGE 0x12378086 ;; i440FX PCI bridge
+// GMCH is emulated by Bochs and QEMU
+//#define PCI_FIXED_HOST_BRIDGE 0x29c08086 ;; Q35 GMCH host PCI bridge
// #20 is dec 20
// #$20 is hex 20 = 32
--
1.6.0.2
^ permalink raw reply related [flat|nested] 20+ messages in thread* [Qemu-devel] [PATCH 10/14] pcibos: add mcfg entry to ACPI table for q35 pcie.
2009-09-30 10:18 [Qemu-devel] [PATCH 00/14] pcbios: support q35 chipset Isaku Yamahata
` (8 preceding siblings ...)
2009-09-30 10:18 ` [Qemu-devel] [PATCH 09/14] pcbios: comment out PCI_FIXED_HOST_BRIDGE for gmch host pci bridge to undef Isaku Yamahata
@ 2009-09-30 10:18 ` Isaku Yamahata
2009-09-30 10:18 ` [Qemu-devel] [PATCH 11/14] pcbios: reserve mcfg area by e820 for linux to use mcfg Isaku Yamahata
` (4 subsequent siblings)
14 siblings, 0 replies; 20+ messages in thread
From: Isaku Yamahata @ 2009-09-30 10:18 UTC (permalink / raw)
To: qemu-devel, anthony; +Cc: yamahata
add mcfg entry to ACPI table for q35 pcie.
Signed-off-by: Isaku Yamahata <yamahata@valinux.co.jp>
---
rombios32.c | 88 ++++++++++++++++++++++++++++++++++++++++++++++++++++++-----
1 files changed, 81 insertions(+), 7 deletions(-)
diff --git a/rombios32.c b/rombios32.c
index f7e906f..3259433 100644
--- a/rombios32.c
+++ b/rombios32.c
@@ -715,6 +715,13 @@ void smp_probe(void)
#define Q35_HOST_BRIDGE_PAM0 0x90
#define Q35_HOST_BRDIGE_SMRAM 0x9d
+#define Q35_HOST_BRIDGE_PCIEXBAR 0x60
+#define Q35_HOST_BRIDGE_PCIEXBAR_ADDR 0xe0000000
+#define Q35_HOST_BRIDGE_PCIEXBAREN ((uint64_t)1)
+#define Q35_HOST_PCIE_PCI_SEGMENT 0
+#define Q35_HOST_PCIE_START_BUS_NUMBER 0
+#define Q35_HOST_PCIE_END_BUS_NUMBER 255
+
#define PCI_DEVICE_ID_INTEL_ICH9_LPC 0x2918
#define ICH9_LPC_PMBASE 0x40
#define ICH9_PMBASE_SMI_EN 0x30
@@ -890,6 +897,18 @@ static void mch_bios_lock_shadow_ram(PCIDevice *d)
bios_lock_shadow_ram_common(d, Q35_HOST_BRIDGE_PAM0);
}
+static void mch_pcie_init(PCIDevice *d)
+{
+ uint64_t val = Q35_HOST_BRIDGE_PCIEXBAR_ADDR | Q35_HOST_BRIDGE_PCIEXBAREN;
+ uint32_t upper = val >> 32;
+ uint32_t lower = val & 0xffffffff;
+
+ /* at first disable the region. and then update/enable it. */
+ pci_config_writel(d, Q35_HOST_BRIDGE_PCIEXBAR, 0);
+ pci_config_writel(d, Q35_HOST_BRIDGE_PCIEXBAR + 4, upper);
+ pci_config_writel(d, Q35_HOST_BRIDGE_PCIEXBAR, lower);
+}
+
static void bios_lock_shadow_ram(void)
{
if (i440_found)
@@ -942,6 +961,7 @@ static void pci_bios_init_bridges(PCIDevice *d)
device_id == PCI_DEVICE_ID_INTEL_Q35_MCH) {
/* ich9 PCI host bridge */
mch_bios_shadow_init(d);
+ mch_pcie_init(d);
}
}
@@ -1481,7 +1501,7 @@ struct rsdt_descriptor_rev1
{
ACPI_TABLE_HEADER_DEF /* ACPI common table header */
#ifdef BX_QEMU
- uint32_t table_offset_entry [5]; /* Array of pointers to other */
+ uint32_t table_offset_entry [6]; /* Array of pointers to other */
#else
uint32_t table_offset_entry [3]; /* Array of pointers to other */
#endif
@@ -1708,6 +1728,22 @@ struct madt_int_override
} __attribute__((__packed__));
#endif
+/* PCI fw r3.0 MCFG table. stolen from linux header file */
+struct acpi_table_mcfg {
+ ACPI_TABLE_HEADER_DEF;
+ uint8_t reserved[8];
+} __attribute__((__packed__));
+
+/* Subtable */
+struct acpi_mcfg_allocation {
+ uint64_t address; /* Base address, processor-relative */
+ uint16_t pci_segment; /* PCI segment group number */
+ uint8_t start_bus_number; /* Starting PCI Bus number */
+ uint8_t end_bus_number; /* Final PCI Bus number */
+ uint32_t reserved;
+} __attribute__((__packed__));
+
+
#include "acpi-dsdt.hex"
static inline uint16_t cpu_to_le16(uint16_t x)
@@ -1832,12 +1868,17 @@ void acpi_bios_init(void)
struct system_resource_affinity_table *srat;
struct acpi_20_hpet *hpet;
uint32_t hpet_addr;
+ uint32_t mcfg_addr = 0;
+ uint32_t mcfg_size;
+ struct acpi_table_mcfg *mcfg = NULL;
+ struct acpi_mcfg_allocation *mcfg_alloc = NULL;
#endif
uint32_t base_addr, rsdt_addr, fadt_addr, addr, facs_addr, dsdt_addr, ssdt_addr;
uint32_t acpi_tables_size, madt_addr, madt_size, rsdt_size;
uint32_t srat_addr,srat_size;
uint16_t i, external_tables;
int nb_numa_nodes;
+ int nb_entry;
/* reserve memory space for tables */
#ifdef BX_USE_EBDA_TABLES
@@ -1916,6 +1957,16 @@ void acpi_bios_init(void)
hpet_addr = addr;
hpet = (void *)(addr);
addr += sizeof(*hpet);
+
+ mcfg_size = 0;
+ if (mch_found) {
+ addr = (addr + 7) & ~7;
+ mcfg_addr = addr;
+ mcfg = (void*)addr;
+ mcfg_alloc = (void*)(addr + sizeof(*mcfg));
+ mcfg_size = sizeof(*mcfg) + sizeof(*mcfg_alloc);
+ addr += mcfg_size;
+ }
#endif
/* RSDP */
@@ -2117,19 +2168,42 @@ void acpi_bios_init(void)
if(addr >= ram_size)
BX_PANIC("ACPI table overflow\n");
}
+
+ /* MCFG */
+ if (mch_found) {
+ memset(mcfg, 0, mcfg_size);
+ mcfg_alloc->address = Q35_HOST_BRIDGE_PCIEXBAR_ADDR;
+ mcfg_alloc->pci_segment = Q35_HOST_PCIE_PCI_SEGMENT;
+ mcfg_alloc->start_bus_number = Q35_HOST_PCIE_START_BUS_NUMBER;
+ mcfg_alloc->end_bus_number = Q35_HOST_PCIE_END_BUS_NUMBER;
+
+ acpi_build_table_header((struct acpi_table_header *)mcfg,
+ "MCFG", mcfg_size, 1);
+ }
#endif
/* RSDT */
- rsdt->table_offset_entry[0] = cpu_to_le32(fadt_addr);
- rsdt->table_offset_entry[1] = cpu_to_le32(madt_addr);
- rsdt->table_offset_entry[2] = cpu_to_le32(ssdt_addr);
+ nb_entry = 0;
+ rsdt->table_offset_entry[nb_entry++] = cpu_to_le32(fadt_addr);
+ rsdt->table_offset_entry[nb_entry++] = cpu_to_le32(madt_addr);
+ rsdt->table_offset_entry[nb_entry++] = cpu_to_le32(ssdt_addr);
#ifdef BX_QEMU
- rsdt->table_offset_entry[3] = cpu_to_le32(hpet_addr);
+ rsdt->table_offset_entry[nb_entry++] = cpu_to_le32(hpet_addr);
if (nb_numa_nodes > 0)
- rsdt->table_offset_entry[4] = cpu_to_le32(srat_addr);
+ rsdt->table_offset_entry[nb_entry++] = cpu_to_le32(srat_addr);
+ if (mcfg_size > 0)
+ rsdt->table_offset_entry[nb_entry++] = cpu_to_le32(mcfg_addr);
#endif
+ if (sizeof(rsdt->table_offset_entry) /
+ sizeof(rsdt->table_offset_entry[0]) >= nb_entry)
+ BX_INFO("rdst table_offset_entry size is too short %d."
+ "increase it to %d.\n",
+ sizeof(rsdt->table_offset_entry) /
+ sizeof(rsdt->table_offset_entry[0]),
+ nb_entry);
acpi_build_table_header((struct acpi_table_header *)rsdt, "RSDT",
- rsdt_size - (nb_numa_nodes > 0? 0: sizeof(uint32_t)), 1);
+ offsetof(struct rsdt_descriptor_rev1, table_offset_entry) +
+ nb_entry * sizeof(uint32_t), 1);
acpi_tables_size = addr - base_addr;
--
1.6.0.2
^ permalink raw reply related [flat|nested] 20+ messages in thread* [Qemu-devel] [PATCH 11/14] pcbios: reserve mcfg area by e820 for linux to use mcfg.
2009-09-30 10:18 [Qemu-devel] [PATCH 00/14] pcbios: support q35 chipset Isaku Yamahata
` (9 preceding siblings ...)
2009-09-30 10:18 ` [Qemu-devel] [PATCH 10/14] pcibos: add mcfg entry to ACPI table for q35 pcie Isaku Yamahata
@ 2009-09-30 10:18 ` Isaku Yamahata
2009-09-30 10:18 ` [Qemu-devel] [PATCH 12/14] pcbios: make pci bar initialization to be aware of preferchable memory Isaku Yamahata
` (3 subsequent siblings)
14 siblings, 0 replies; 20+ messages in thread
From: Isaku Yamahata @ 2009-09-30 10:18 UTC (permalink / raw)
To: qemu-devel, anthony; +Cc: yamahata
reserve mcfg area by e820.
Linux checks whether e820 covers mcfg area. If not, linux won't to use
MCFG.
Signed-off-by: Isaku Yamahata <yamahata@valinux.co.jp>
---
.gitignore | 1 +
Makefile | 7 +++++--
rombios.c | 48 ++++++++++++++++++++++++++++++++++++++++++++++++
rombios32.c | 31 +++++++++++++++++++++++++++----
4 files changed, 81 insertions(+), 6 deletions(-)
diff --git a/.gitignore b/.gitignore
index 86e696c..8d8536f 100644
--- a/.gitignore
+++ b/.gitignore
@@ -17,3 +17,4 @@ rombios32start.o
rombiosl.s
rombiosl.sym
rombiosl.txt
+mcfg.h
diff --git a/Makefile b/Makefile
index 22599fa..82bf1e8 100644
--- a/Makefile
+++ b/Makefile
@@ -46,7 +46,7 @@ clean:
$(RM) *.o *.a *.s _rombios*_.c rombios*.txt rombios*.sym *.aml *.hex
$(RM) usage biossums rombios16.bin
$(RM) rombios32.bin rombios32.out
- $(RM) BIOS-bochs-latest BIOS-bochs-legacy
+ $(RM) BIOS-bochs-latest BIOS-bochs-legacy mcfg.h
dist-clean: clean
$(RM) Makefile
@@ -75,6 +75,9 @@ rombios16.bin: rombios.c apmbios.S biossums rombios.h makesym.perl
./biossums rombios16.bin
$(RM) _rombios_.s
+rombios.sym: rombios16.bin
+mcfg.h: rombios.sym
+ awk '/_mcfg_/{print "#define "toupper($$2)" ((uint32_t *)0x"$$1")"}' $< > $@
rombios32.bin: rombios32.out rombios.h
$(OBJCOPY) -O binary $< $@
@@ -83,7 +86,7 @@ rombios32.bin: rombios32.out rombios.h
rombios32.out: rombios32start.o rombios32.o rombios32.ld
$(LD) -o $@ -T $(SRC_PATH)/rombios32.ld rombios32start.o rombios32.o
-rombios32.o: rombios32.c acpi-dsdt.hex
+rombios32.o: rombios32.c acpi-dsdt.hex mcfg.h
$(GCC32) -O2 -Wall -I. -c -o $@ $<
acpi-dsdt.hex: acpi-dsdt.dsl
diff --git a/rombios.c b/rombios.c
index 2b94d76..2d42f9e 100644
--- a/rombios.c
+++ b/rombios.c
@@ -4488,6 +4488,13 @@ void set_e820_range(ES, DI, start, end, extra_start, extra_end, type)
write_word(ES, DI+18, 0x0);
}
+#if BX_ROMBIOS32
+extern Bit32u rombios32_mcfg_addr; /* addr: lsb 32 bit */
+extern Bit32u rombios32_extra_mcfg_addr; /* addr: msb 32 bit */
+extern Bit32u rombios32_mcfg_end; /* size: lsb 32b it */
+extern Bit32u rombios32_extra_mcfg_end; /* size: msb 32 bit */
+#endif
+
void
int15_function32(regs, ES, DS, FLAGS)
pushad_regs_t regs; // REGS pushed via pushad
@@ -4497,6 +4504,10 @@ int15_function32(regs, ES, DS, FLAGS)
Bit32u extra_lowbits_memory_size=0;
Bit16u CX,DX;
Bit32u extra_highbits_memory_size=0;
+ Bit32u mcfg_addr;
+ Bit32u extra_mcfg_addr;
+ Bit32u mcfg_end;
+ Bit32u extra_mcfg_end;
BX_DEBUG_INT15("int15 AX=%04x\n",regs.u.r16.ax);
@@ -4577,6 +4588,14 @@ ASM_END
extra_lowbits_memory_size *= 1024;
extra_highbits_memory_size = inb_cmos(0x5d);
+#if BX_ROMBIOS32
+ mcfg_addr = read_dword(0xf000, &rombios32_mcfg_addr);
+ extra_mcfg_addr = read_dword(0xf000,
+ &rombios32_extra_mcfg_addr);
+ mcfg_end = read_dword(0xf000, &rombios32_mcfg_end);
+ extra_mcfg_end = read_dword(0xf000,
+ &rombios32_extra_mcfg_end);
+#endif
switch(regs.u.r16.bx)
{
case 0:
@@ -4619,6 +4638,10 @@ ASM_END
0xfffc0000L, 0x00000000L ,0L, 0L, 2);
if (extra_highbits_memory_size || extra_lowbits_memory_size)
regs.u.r32.ebx = 6;
+#if BX_ROMBIOS32
+ else if (mcfg_end || extra_mcfg_end)
+ regs.u.r32.ebx = 7;
+#endif
else
regs.u.r32.ebx = 0;
break;
@@ -4627,8 +4650,25 @@ ASM_END
set_e820_range(ES, regs.u.r16.di, 0x00000000L,
extra_lowbits_memory_size, 1, extra_highbits_memory_size
+ 1, 1);
+#if BX_ROMBIOS32
+ if (mcfg_end || extra_mcfg_end)
+ regs.u.r32.ebx = 7;
+ else
+ regs.u.r32.ebx = 0;
+#else
+ regs.u.r32.ebx = 0;
+#endif
+ break;
+#if BX_ROMBIOS32
+ case 7:
+ /* MCFG reserved area */
+ set_e820_range(ES, regs.u.r16.di,
+ mcfg_addr, mcfg_end,
+ extra_mcfg_addr, extra_mcfg_end,
+ 2);
regs.u.r32.ebx = 0;
break;
+#endif
default: /* AX=E820, DX=534D4150, BX unrecognized */
goto int15_unimplemented;
break;
@@ -10364,6 +10404,14 @@ post_init_pic:
;; the following area can be used to write dynamically generated tables
.align 16
+_rombios32_mcfg_addr:
+ dd 0
+_rombios32_extra_mcfg_addr:
+ dd 0
+_rombios32_mcfg_end:
+ dd 0
+_rombios32_extra_mcfg_end:
+ dd 0
bios_table_area_start:
dd 0xaafb4442
dd bios_table_area_end - bios_table_area_start - 8;
diff --git a/rombios32.c b/rombios32.c
index 3259433..e22307e 100644
--- a/rombios32.c
+++ b/rombios32.c
@@ -32,6 +32,8 @@ typedef unsigned short uint16_t;
typedef unsigned int uint32_t;
typedef unsigned long long uint64_t;
+#include "mcfg.h"
+
/* if true, put the MP float table and ACPI RSDT in EBDA and the MP
table in RAM. Unfortunately, Linux has bugs with that, so we prefer
to modify the BIOS in shadow RAM */
@@ -716,6 +718,7 @@ void smp_probe(void)
#define Q35_HOST_BRDIGE_SMRAM 0x9d
#define Q35_HOST_BRIDGE_PCIEXBAR 0x60
+#define Q35_HOST_BRIDGE_PCIEXBAR_SIZE (256 * 1024 * 1024)
#define Q35_HOST_BRIDGE_PCIEXBAR_ADDR 0xe0000000
#define Q35_HOST_BRIDGE_PCIEXBAREN ((uint64_t)1)
#define Q35_HOST_PCIE_PCI_SEGMENT 0
@@ -899,14 +902,34 @@ static void mch_bios_lock_shadow_ram(PCIDevice *d)
static void mch_pcie_init(PCIDevice *d)
{
- uint64_t val = Q35_HOST_BRIDGE_PCIEXBAR_ADDR | Q35_HOST_BRIDGE_PCIEXBAREN;
- uint32_t upper = val >> 32;
- uint32_t lower = val & 0xffffffff;
+ uint64_t addr = Q35_HOST_BRIDGE_PCIEXBAR_ADDR | Q35_HOST_BRIDGE_PCIEXBAREN;
+ uint32_t upper = addr >> 32;
+ uint32_t lower = addr & 0xffffffff;
+ uint64_t end;
+ uint32_t upper_end;
+ uint32_t lower_end;
/* at first disable the region. and then update/enable it. */
pci_config_writel(d, Q35_HOST_BRIDGE_PCIEXBAR, 0);
pci_config_writel(d, Q35_HOST_BRIDGE_PCIEXBAR + 4, upper);
pci_config_writel(d, Q35_HOST_BRIDGE_PCIEXBAR, lower);
+
+ /* for e820 */
+ addr = Q35_HOST_BRIDGE_PCIEXBAR_ADDR;
+ upper = addr >> 32;
+ lower = addr & 0xffffffff;
+ end = addr + Q35_HOST_BRIDGE_PCIEXBAR_SIZE;
+ upper_end = end >> 32;
+ lower_end = end & 0xffffffff;
+
+ /* This function must be called after shadow ram initialization
+ * otherwise those area are read only as ROM so that those
+ * stores are lost.
+ */
+ *_ROMBIOS32_MCFG_ADDR = lower;
+ *_ROMBIOS32_EXTRA_MCFG_ADDR = upper;
+ *_ROMBIOS32_MCFG_END = lower_end;
+ *_ROMBIOS32_EXTRA_MCFG_END = upper_end;
}
static void bios_lock_shadow_ram(void)
@@ -961,7 +984,7 @@ static void pci_bios_init_bridges(PCIDevice *d)
device_id == PCI_DEVICE_ID_INTEL_Q35_MCH) {
/* ich9 PCI host bridge */
mch_bios_shadow_init(d);
- mch_pcie_init(d);
+ mch_pcie_init(d); /* must be after shadow init */
}
}
--
1.6.0.2
^ permalink raw reply related [flat|nested] 20+ messages in thread* [Qemu-devel] [PATCH 12/14] pcbios: make pci bar initialization to be aware of preferchable memory.
2009-09-30 10:18 [Qemu-devel] [PATCH 00/14] pcbios: support q35 chipset Isaku Yamahata
` (10 preceding siblings ...)
2009-09-30 10:18 ` [Qemu-devel] [PATCH 11/14] pcbios: reserve mcfg area by e820 for linux to use mcfg Isaku Yamahata
@ 2009-09-30 10:18 ` Isaku Yamahata
2009-09-30 10:18 ` [Qemu-devel] [PATCH 13/14] pcbios: change acpi dsdt for q35 chipset Isaku Yamahata
` (2 subsequent siblings)
14 siblings, 0 replies; 20+ messages in thread
From: Isaku Yamahata @ 2009-09-30 10:18 UTC (permalink / raw)
To: qemu-devel, anthony; +Cc: yamahata
make pci bar initialization to be aware of preferchable memory.
Signed-off-by: Isaku Yamahata <yamahata@valinux.co.jp>
---
rombios32.c | 256 +++++++++++++++++++++++++++++++++++++++++++++++++----------
1 files changed, 213 insertions(+), 43 deletions(-)
diff --git a/rombios32.c b/rombios32.c
index e22307e..c334db2 100644
--- a/rombios32.c
+++ b/rombios32.c
@@ -699,7 +699,28 @@ void smp_probe(void)
#define PCI_COMMAND 0x04 /* 16 bits */
#define PCI_COMMAND_IO 0x1 /* Enable response in I/O space */
#define PCI_COMMAND_MEMORY 0x2 /* Enable response in Memory space */
+#define PCI_COMMAND_MASTER 0x4 /* Enable bus master */
#define PCI_CLASS_DEVICE 0x0a /* Device class */
+#define PCI_CLASS_BRIDGE_PCI 0x0604 /* pci bridge */
+#define PCI_PRIMARY_BUS 0x18
+#define PCI_SECONDARY_BUS 0x19
+#define PCI_SUBORDINATE_BUS 0x1a
+#define PCI_IO_BASE 0x1c
+#define PCI_IO_LIMIT 0x1d
+#define PCI_IO_SHIFT 8
+#define PCI_MEMORY_BASE 0x20
+#define PCI_MEMORY_LIMIT 0x22
+#define PCI_MEMORY_SHIFT 16
+#define PCI_IO_BASE_UPPER16 0x30
+#define PCI_IO_LIMIT_UPPER16 0x32
+
+#define PCI_PREF_MEMORY_BASE 0x24 /* Prefetchable memory range behind */
+#define PCI_PREF_MEMORY_LIMIT 0x26
+#define PCI_PREF_MEMORY_SHIFT 16
+#define PCI_PREF_BASE_UPPER32 0x28 /* Upper half of prefetchable memory range */
+#define PCI_PREF_LIMIT_UPPER32 0x2c
+
+
#define PCI_INTERRUPT_LINE 0x3c /* 8 bits */
#define PCI_INTERRUPT_PIN 0x3d /* 8 bits */
#define PCI_MIN_GNT 0x3e /* 8 bits */
@@ -1117,10 +1138,183 @@ static void pci_align_addr(uint32_t *paddr, uint32_t size)
*paddr = (*paddr + size - 1) & ~(size - 1);
}
+static uint32_t pci_bios_allocate_range(PCIDevice *d, int region_num)
+{
+ uint32_t *paddr;
+ int ofs;
+ uint32_t val, size;
+
+ if (region_num == PCI_ROM_SLOT) {
+ ofs = 0x30;
+ pci_config_writel(d, ofs, 0xfffffffe);
+ } else {
+ ofs = 0x10 + region_num * 4;
+ pci_config_writel(d, ofs, 0xffffffff);
+ }
+
+ val = pci_config_readl(d, ofs);
+ if (val != 0) {
+ size = (~(val & ~0xf)) + 1;
+ if (val & PCI_ADDRESS_SPACE_IO)
+ paddr = &pci_bios_io_addr;
+ else if (val & PCI_ADDRESS_SPACE_MEM_PREFETCH)
+ paddr = &pci_bios_prefmem_addr;
+ else if (size >= 0x04000000 || d->bus != 0)
+ paddr = &pci_bios_bigmem_addr;
+ else
+ paddr = &pci_bios_mem_addr;
+ pci_align_addr(paddr, size);
+ pci_set_io_region_addr(d, region_num, *paddr);
+ *paddr += size;
+ }
+ return val & (PCI_ADDRESS_SPACE_IO |
+ PCI_ADDRESS_SPACE_TYPE_MASK |
+ PCI_ADDRESS_SPACE_MEM_PREFETCH);
+}
+
+void pci_for_each_device_in_bus(int bus, void (*init_func)(PCIDevice *d))
+{
+ PCIDevice d1, *d = &d1;
+ int devfn;
+ uint16_t vendor_id, device_id;
+
+ for(devfn = 0; devfn < 256; devfn++) {
+ d->bus = bus;
+ d->devfn = devfn;
+ vendor_id = pci_config_readw(d, PCI_VENDOR_ID);
+ device_id = pci_config_readw(d, PCI_DEVICE_ID);
+ if (vendor_id != 0xffff || device_id != 0xffff) {
+ init_func(d);
+ }
+ }
+}
+
+static void pci_bios_init_device(PCIDevice *d);
+
+static void pci_bios_init_device_bridge(PCIDevice *d)
+{
+ int i;
+ uint32_t br_io_base;
+ uint32_t br_io_end;
+ uint32_t br_bigmem_base;
+ uint32_t br_bigmem_end;
+ uint32_t br_prefmem_base;
+ uint32_t br_prefmem_end;
+ uint16_t cmd;
+
+ static uint8_t bus = 0;
+ uint8_t pribus;
+ uint8_t secbus;
+ uint8_t subbus;
+
+ for (i = 0; i < 2; i++) {
+ pci_bios_allocate_range(d, i);
+ }
+
+ pribus = pci_config_readb(d, PCI_PRIMARY_BUS);
+ if (pribus != d->bus) {
+ pci_config_writeb(d, PCI_PRIMARY_BUS, d->bus);
+ BX_INFO("PCI: pribus = 0x%x -> 0x%x\n", pribus, d->bus);
+ } else {
+ BX_INFO("PCI: pribus = 0x%x\n", pribus);
+ }
+
+ secbus = pci_config_readb(d, PCI_SECONDARY_BUS);
+ if (secbus == 0 || bus > secbus) {
+ bus++;
+ pci_config_writeb(d, PCI_SECONDARY_BUS, bus);
+ BX_INFO("PCI: secbus changed = 0x%x -> 0x%x\n", secbus, bus);
+ } else if (bus < secbus) {
+ bus = secbus;
+ BX_INFO("PCI: secbus = 0x%x\n", bus);
+ }
+
+ /* set to max for access to all subordinate buses.
+ later set it to accurate value */
+ subbus = pci_config_readb(d, PCI_SUBORDINATE_BUS);;
+ pci_config_writeb(d, PCI_SUBORDINATE_BUS, 256);
+
+ /* IO BASE is assumed to be 16 bit */
+ pci_align_addr(&pci_bios_io_addr, 4096);
+ pci_align_addr(&pci_bios_bigmem_addr, 1UL << 20);
+ pci_align_addr(&pci_bios_prefmem_addr, 1UL << 20);
+ br_io_base = pci_bios_io_addr;
+ br_bigmem_base = pci_bios_bigmem_addr;
+ br_prefmem_base = pci_bios_prefmem_addr;
+ pci_for_each_device_in_bus(bus, pci_bios_init_device);
+ pci_align_addr(&pci_bios_io_addr, 4096);
+ pci_align_addr(&pci_bios_bigmem_addr, 1UL << 20);
+ pci_align_addr(&pci_bios_prefmem_addr, 1UL << 20);
+
+ if (subbus != bus) {
+ BX_INFO("PCI: subordinate bus = 0x%x -> 0x%x\n", subbus, bus);
+ } else {
+ BX_INFO("PCI: subordinate bus = 0x%x\n", subbus);
+ }
+ if (subbus > bus){
+ bus = subbus;
+ }
+ pci_config_writeb(d, PCI_SUBORDINATE_BUS, bus);
+
+ br_io_end = pci_bios_io_addr;
+ if (br_io_end == br_io_base) {
+ br_io_base = 0xffff;
+ br_io_end = 1;
+ }
+ pci_config_writeb(d, PCI_IO_BASE,
+ br_io_base >> PCI_IO_SHIFT);
+ pci_config_writew(d, PCI_IO_BASE_UPPER16, 0);
+ pci_config_writeb(d, PCI_IO_LIMIT,
+ (br_io_end - 1) >> PCI_IO_SHIFT);
+ pci_config_writew(d, PCI_IO_LIMIT_UPPER16, 0);
+
+ br_bigmem_end = pci_bios_bigmem_addr;
+ if (br_bigmem_end == br_bigmem_base) {
+ br_bigmem_base = 0xffffffff;
+ br_bigmem_end = 1;
+ }
+ pci_config_writew(d, PCI_MEMORY_BASE,
+ br_bigmem_base >> PCI_MEMORY_SHIFT);
+ pci_config_writew(d, PCI_MEMORY_LIMIT,
+ (br_bigmem_end -1) >> PCI_MEMORY_SHIFT);
+
+ br_prefmem_end = pci_bios_prefmem_addr;
+ if (br_prefmem_end == br_prefmem_base) {
+ br_prefmem_base = 0xffffffff;
+ br_prefmem_end = 1;
+ }
+ pci_config_writew(d, PCI_PREF_MEMORY_BASE,
+ br_prefmem_base >> PCI_PREF_MEMORY_SHIFT);
+ pci_config_writew(d, PCI_PREF_MEMORY_LIMIT,
+ (br_prefmem_end - 1) >> PCI_PREF_MEMORY_SHIFT);
+ pci_config_writel(d, PCI_PREF_BASE_UPPER32, 0);
+ pci_config_writel(d, PCI_PREF_LIMIT_UPPER32, 0);
+
+ BX_INFO("PCI: br subord bus 0x%x\n", bus);
+ BX_INFO("PCI: br IO = [0x%lx, 0x%lx)\n", br_io_base, br_io_end);
+ BX_INFO("PCI: br MEM = [0x%lx, 0x%lx)\n",
+ br_bigmem_base, br_bigmem_end);
+ BX_INFO("PCI: br PREF = [0x%lx, 0x%lx)\n",
+ br_prefmem_base, br_prefmem_end);
+
+ cmd = pci_config_readw(d, PCI_COMMAND);
+ if (br_io_end > br_io_base) {
+ cmd |= PCI_COMMAND_IO;
+ } else {
+ cmd &= ~PCI_COMMAND_IO;
+ }
+ cmd &= ~PCI_COMMAND_MEMORY;
+ if (br_bigmem_end > br_bigmem_base ||
+ br_prefmem_end > br_prefmem_base) {
+ cmd |= PCI_COMMAND_MEMORY;
+ }
+ cmd |= PCI_COMMAND_MASTER;
+ pci_config_writew(d, PCI_COMMAND, cmd);
+}
+
static void pci_bios_init_device(PCIDevice *d)
{
int class;
- uint32_t *paddr;
int i, pin, pic_irq, vendor_id, device_id;
class = pci_config_readw(d, PCI_CLASS_DEVICE);
@@ -1148,8 +1342,14 @@ static void pci_bios_init_device(PCIDevice *d)
case 0x0300: /* Display controller - VGA compatible controller */
if (vendor_id != 0x1234)
goto default_map;
- /* VGA: map frame buffer to default Bochs VBE address */
- pci_set_io_region_addr(d, 0, 0xE0000000);
+ if (mch_found) {
+ /* avoid MCFG area. use [0xf8000000, 0xf8800000)
+ 0x2000000 = 8M VRAM_SIZE */
+ pci_set_io_region_addr(d, 0, 0xf8000000);
+ } else {
+ /* VGA: map frame buffer to default Bochs VBE address */
+ pci_set_io_region_addr(d, 0, 0xE0000000);
+ }
break;
case 0x0800: /* Generic system peripheral - PIC */
if (vendor_id == PCI_VENDOR_ID_IBM) {
@@ -1167,35 +1367,14 @@ static void pci_bios_init_device(PCIDevice *d)
pci_set_io_region_addr(d, 0, 0x80800000);
}
break;
+ case PCI_CLASS_BRIDGE_PCI:
+ pci_bios_init_device_bridge(d);
+ break;
default:
default_map:
/* default memory mappings */
for(i = 0; i < PCI_NUM_REGIONS; i++) {
- int ofs;
- uint32_t val, size ;
-
- if (i == PCI_ROM_SLOT) {
- ofs = 0x30;
- pci_config_writel(d, ofs, 0xfffffffe);
- } else {
- ofs = 0x10 + i * 4;
- pci_config_writel(d, ofs, 0xffffffff);
- }
- val = pci_config_readl(d, ofs);
- if (val != 0) {
- size = (~(val & ~0xf)) + 1;
- if (val & PCI_ADDRESS_SPACE_IO)
- paddr = &pci_bios_io_addr;
- else if (val & PCI_ADDRESS_SPACE_MEM_PREFETCH)
- paddr = &pci_bios_prefmem_addr;
- else if (size >= 0x04000000)
- paddr = &pci_bios_bigmem_addr;
- else
- paddr = &pci_bios_mem_addr;
- pci_align_addr(paddr, size);
- pci_set_io_region_addr(d, i, *paddr);
- *paddr += size;
- }
+ uint32_t val = pci_bios_allocate_range(d, i);
/* 64bit bar */
if (!(val & PCI_ADDRESS_SPACE_IO) &&
@@ -1247,20 +1426,10 @@ static void pci_bios_init_device(PCIDevice *d)
void pci_for_each_device(void (*init_func)(PCIDevice *d))
{
- PCIDevice d1, *d = &d1;
- int bus, devfn;
- uint16_t vendor_id, device_id;
+ int bus;
- for(bus = 0; bus < 1; bus++) {
- for(devfn = 0; devfn < 256; devfn++) {
- d->bus = bus;
- d->devfn = devfn;
- vendor_id = pci_config_readw(d, PCI_VENDOR_ID);
- device_id = pci_config_readw(d, PCI_DEVICE_ID);
- if (vendor_id != 0xffff || device_id != 0xffff) {
- init_func(d);
- }
- }
+ for(bus = 0; bus < 256; bus++) {
+ pci_for_each_device_in_bus(bus, init_func);
}
}
@@ -1274,12 +1443,13 @@ void pci_bios_init(void)
pci_bios_prefmem_addr = pci_bios_bigmem_addr + 0x08000000;
pci_align_addr(&pci_bios_prefmem_addr, 0x08000000);
if (pci_bios_prefmem_addr >= 0xe0000000) {
- pci_bios_prefmem_addr = 0xf800000;
+ /* 0x2000000 = 8M vga frame buffer */
+ pci_bios_prefmem_addr = 0xf800000 + 0x2000000;
}
pci_for_each_device(pci_bios_init_bridges);
- pci_for_each_device(pci_bios_init_device);
+ pci_for_each_device_in_bus(0, pci_bios_init_device);
}
/****************************************************/
--
1.6.0.2
^ permalink raw reply related [flat|nested] 20+ messages in thread* [Qemu-devel] [PATCH 13/14] pcbios: change acpi dsdt for q35 chipset.
2009-09-30 10:18 [Qemu-devel] [PATCH 00/14] pcbios: support q35 chipset Isaku Yamahata
` (11 preceding siblings ...)
2009-09-30 10:18 ` [Qemu-devel] [PATCH 12/14] pcbios: make pci bar initialization to be aware of preferchable memory Isaku Yamahata
@ 2009-09-30 10:18 ` Isaku Yamahata
2009-09-30 10:18 ` [Qemu-devel] [PATCH 14/14] pcibos/acpi dsdt: APIC mode support " Isaku Yamahata
2009-09-30 13:23 ` [Qemu-devel] Re: [PATCH 00/14] pcbios: support " Anthony Liguori
14 siblings, 0 replies; 20+ messages in thread
From: Isaku Yamahata @ 2009-09-30 10:18 UTC (permalink / raw)
To: qemu-devel, anthony; +Cc: yamahata
change acpi dsdt for q35 chipset.
Signed-off-by: Isaku Yamahata <yamahata@valinux.co.jp>
---
Makefile | 2 +-
acpi-dsdt.dsl | 689 +++++++++++++++++++++++++++------------------------------
2 files changed, 327 insertions(+), 364 deletions(-)
diff --git a/Makefile b/Makefile
index 82bf1e8..0f99418 100644
--- a/Makefile
+++ b/Makefile
@@ -90,7 +90,7 @@ rombios32.o: rombios32.c acpi-dsdt.hex mcfg.h
$(GCC32) -O2 -Wall -I. -c -o $@ $<
acpi-dsdt.hex: acpi-dsdt.dsl
- $(CPP) -P $< > acpi-dsdt.dsl.i
+ $(CPP) -x assembler-with-cpp -P $< > acpi-dsdt.dsl.i
$(IASL) -tc -p $@ acpi-dsdt.dsl.i || ($(RM) $@; exit 1)
$(RM) acpi-dsdt.dsl.i
sed -i -e's/^unsigned/const unsigned/' $@
diff --git a/acpi-dsdt.dsl b/acpi-dsdt.dsl
index 56fb787..d75927b 100644
--- a/acpi-dsdt.dsl
+++ b/acpi-dsdt.dsl
@@ -27,19 +27,56 @@ DefinitionBlock (
{
Scope (\)
{
- /* Debug Output */
- OperationRegion (DBG, SystemIO, 0xb044, 0x04)
+ /* Debug Output. 0xb044 is already used by ich9 lpc.
+ so 0xb080 is chosen. */
+ OperationRegion (DBG, SystemIO, 0xb080, 0x04)
Field (DBG, DWordAcc, NoLock, Preserve)
{
DBGL, 32,
}
+
+ /* reserve this io port for gurest OS not to use it */
+ Device (DBG0)
+ {
+ Name(_HID, EISAID("PNP0C02"))
+ Name(_CRS, ResourceTemplate() {
+ IO (Decode16, 0xb080, 0xb080, 0x00, 0x04)
+ })
+ }
}
+ Scope (\_SB)
+ {
+ OperationRegion(PCST, SystemIO, 0xae00, 0x0c)
+ Field (PCST, DWordAcc, NoLock, WriteAsZeros)
+ {
+ PCIU, 32,
+ PCID, 32,
+ B0EJ, 32,
+ }
+ OperationRegion(PCSB, SystemIO, 0xae0c, 0x01)
+ Field (PCSB, AnyAcc, NoLock, WriteAsZeros)
+ {
+ PCIB, 8,
+ }
+
+ /* reserve those io ports for gurest OS not to use it */
+ Device(HP0)
+ {
+ Name(_HID, EISAID("PNP0C02"))
+ Name(_CRS, ResourceTemplate() {
+ IO (Decode16, 0xae00, 0xae00, 0x00, 0x0C)
+ IO (Decode16, 0xae0c, 0xae0c, 0x00, 0x01)
+ })
+ }
+ }
+
/* PCI Bus definition */
Scope(\_SB) {
Device(PCI0) {
- Name (_HID, EisaId ("PNP0A03"))
+ Name (_HID, EisaId ("PNP0A08"))
+ Name (_CID, EisaId ("PNP0A03"))
Name (_ADR, 0x00)
Name (_UID, 1)
Name(_PRT, Package() {
@@ -53,98 +90,97 @@ DefinitionBlock (
Package() { nr##ffff, 2, lnk2, 0 }, \
Package() { nr##ffff, 3, lnk3, 0 }
-#define prt_slot0(nr) prt_slot(nr, LNKD, LNKA, LNKB, LNKC)
-#define prt_slot1(nr) prt_slot(nr, LNKA, LNKB, LNKC, LNKD)
-#define prt_slot2(nr) prt_slot(nr, LNKB, LNKC, LNKD, LNKA)
-#define prt_slot3(nr) prt_slot(nr, LNKC, LNKD, LNKA, LNKB)
- prt_slot0(0x0000),
- prt_slot1(0x0001),
- prt_slot2(0x0002),
- prt_slot3(0x0003),
- prt_slot0(0x0004),
- prt_slot1(0x0005),
- prt_slot2(0x0006),
- prt_slot3(0x0007),
- prt_slot0(0x0008),
- prt_slot1(0x0009),
- prt_slot2(0x000a),
- prt_slot3(0x000b),
- prt_slot0(0x000c),
- prt_slot1(0x000d),
- prt_slot2(0x000e),
- prt_slot3(0x000f),
- prt_slot0(0x0010),
- prt_slot1(0x0011),
- prt_slot2(0x0012),
- prt_slot3(0x0013),
- prt_slot0(0x0014),
- prt_slot1(0x0015),
- prt_slot2(0x0016),
- prt_slot3(0x0017),
- prt_slot0(0x0018),
- prt_slot1(0x0019),
- prt_slot2(0x001a),
- prt_slot3(0x001b),
- prt_slot0(0x001c),
- prt_slot1(0x001d),
- prt_slot2(0x001e),
- prt_slot3(0x001f),
+#define prt_slotD(nr) prt_slot(nr, LNKD, LNKA, LNKB, LNKC)
+#define prt_slotA(nr) prt_slot(nr, LNKA, LNKB, LNKC, LNKD)
+#define prt_slotB(nr) prt_slot(nr, LNKB, LNKC, LNKD, LNKA)
+#define prt_slotC(nr) prt_slot(nr, LNKC, LNKD, LNKA, LNKB)
+
+#define prt_slots(w, x, y, z) \
+ prt_slot##w(0x0000), \
+ prt_slot##x(0x0001), \
+ prt_slot##y(0x0002), \
+ prt_slot##z(0x0003), \
+ prt_slot##w(0x0004), \
+ prt_slot##x(0x0005), \
+ prt_slot##y(0x0006), \
+ prt_slot##z(0x0007), \
+ prt_slot##w(0x0008), \
+ prt_slot##x(0x0009), \
+ prt_slot##y(0x000a), \
+ prt_slot##z(0x000b), \
+ prt_slot##w(0x000c), \
+ prt_slot##x(0x000d), \
+ prt_slot##y(0x000e), \
+ prt_slot##z(0x000f), \
+ prt_slot##w(0x0010), \
+ prt_slot##x(0x0011), \
+ prt_slot##y(0x0012), \
+ prt_slot##z(0x0013), \
+ prt_slot##w(0x0014), \
+ prt_slot##x(0x0015), \
+ prt_slot##y(0x0016), \
+ prt_slot##z(0x0017), \
+ prt_slot##w(0x0018), \
+ prt_slot##x(0x0019), \
+ prt_slot##y(0x001a), \
+ prt_slot##z(0x001b), \
+ prt_slot##w(0x001c), \
+ prt_slot##x(0x001d), \
+ prt_slot##y(0x001e), \
+ prt_slot##z(0x001f),
+
+ prt_slots(D, A, B, C)
})
- OperationRegion(PCST, SystemIO, 0xae00, 0x08)
- Field (PCST, DWordAcc, NoLock, WriteAsZeros)
- {
- PCIU, 32,
- PCID, 32,
+#define hotplug_slot(name, nr, bus) \
+ Device (S##name) { \
+ Name (_ADR, nr##0000) \
+ Method (_EJ0,1) { \
+ Store(bus, \_SB.PCIB) \
+ Store(ShiftLeft(1, nr), \_SB.B0EJ) \
+ Return (0x0) \
+ } \
+ Name (_SUN, name) \
}
- OperationRegion(SEJ, SystemIO, 0xae08, 0x04)
- Field (SEJ, DWordAcc, NoLock, WriteAsZeros)
- {
- B0EJ, 32,
- }
-
-#define hotplug_slot(name, nr) \
- Device (S##name) { \
- Name (_ADR, nr##0000) \
- Method (_EJ0,1) { \
- Store(ShiftLeft(1, nr), B0EJ) \
- Return (0x0) \
- } \
- Name (_SUN, name) \
- }
-
- hotplug_slot(1, 0x0001)
- hotplug_slot(2, 0x0002)
- hotplug_slot(3, 0x0003)
- hotplug_slot(4, 0x0004)
- hotplug_slot(5, 0x0005)
- hotplug_slot(6, 0x0006)
- hotplug_slot(7, 0x0007)
- hotplug_slot(8, 0x0008)
- hotplug_slot(9, 0x0009)
- hotplug_slot(10, 0x000a)
- hotplug_slot(11, 0x000b)
- hotplug_slot(12, 0x000c)
- hotplug_slot(13, 0x000d)
- hotplug_slot(14, 0x000e)
- hotplug_slot(15, 0x000f)
- hotplug_slot(16, 0x0010)
- hotplug_slot(17, 0x0011)
- hotplug_slot(18, 0x0012)
- hotplug_slot(19, 0x0013)
- hotplug_slot(20, 0x0014)
- hotplug_slot(21, 0x0015)
- hotplug_slot(22, 0x0016)
- hotplug_slot(23, 0x0017)
- hotplug_slot(24, 0x0018)
- hotplug_slot(25, 0x0019)
- hotplug_slot(26, 0x001a)
- hotplug_slot(27, 0x001b)
- hotplug_slot(28, 0x001c)
- hotplug_slot(29, 0x001d)
- hotplug_slot(30, 0x001e)
- hotplug_slot(31, 0x001f)
+#define hotplug_slots1(bus) \
+ hotplug_slot(1, 0x0001, bus) \
+ hotplug_slot(2, 0x0002, bus) \
+ hotplug_slot(3, 0x0003, bus) \
+ hotplug_slot(4, 0x0004, bus) \
+ hotplug_slot(5, 0x0005, bus) \
+ hotplug_slot(6, 0x0006, bus) \
+ hotplug_slot(7, 0x0007, bus) \
+ hotplug_slot(8, 0x0008, bus) \
+ hotplug_slot(9, 0x0009, bus) \
+ hotplug_slot(10, 0x000a, bus) \
+ hotplug_slot(11, 0x000b, bus) \
+ hotplug_slot(12, 0x000c, bus) \
+ hotplug_slot(13, 0x000d, bus) \
+ hotplug_slot(14, 0x000e, bus) \
+ hotplug_slot(15, 0x000f, bus) \
+ hotplug_slot(16, 0x0010, bus) \
+ hotplug_slot(17, 0x0011, bus) \
+ hotplug_slot(18, 0x0012, bus) \
+ hotplug_slot(19, 0x0013, bus) \
+ hotplug_slot(20, 0x0014, bus) \
+ hotplug_slot(21, 0x0015, bus) \
+ hotplug_slot(22, 0x0016, bus) \
+ hotplug_slot(23, 0x0017, bus) \
+ hotplug_slot(24, 0x0018, bus) \
+ hotplug_slot(25, 0x0019, bus) \
+ hotplug_slot(26, 0x001a, bus) \
+ hotplug_slot(27, 0x001b, bus) \
+ hotplug_slot(28, 0x001c, bus) \
+ hotplug_slot(29, 0x001d, bus) \
+ hotplug_slot(30, 0x001e, bus) \
+ hotplug_slot(31, 0x001f, bus)
+
+#define hotplug_slots(bus) \
+ hotplug_slot(0, 0x0000, bus) \
+ hotplug_slots1(bus)
+
+ hotplug_slots1(0)
Name (_CRS, ResourceTemplate ()
{
@@ -191,26 +227,6 @@ DefinitionBlock (
,, , AddressRangeMemory, TypeStatic)
})
}
-#ifdef BX_QEMU
- Device(HPET) {
- Name(_HID, EISAID("PNP0103"))
- Name(_UID, 0)
- Method (_STA, 0, NotSerialized) {
- Return(0x0F)
- }
- Name(_CRS, ResourceTemplate() {
- DWordMemory(
- ResourceConsumer, PosDecode, MinFixed, MaxFixed,
- NonCacheable, ReadWrite,
- 0x00000000,
- 0xFED00000,
- 0xFED003FF,
- 0x00000000,
- 0x00000400 /* 1K memory: FED00000 - FED003FF */
- )
- })
- }
-#endif
}
Scope(\_SB.PCI0) {
@@ -230,13 +246,68 @@ DefinitionBlock (
}
}
- /* PIIX3 ISA bridge */
- Device (ISA) {
- Name (_ADR, 0x00010000)
- /* PIIX PCI to ISA irq remapping */
- OperationRegion (P40C, PCI_Config, 0x60, 0x04)
+ /* PCI D31:f0 LPC ISA bridge */
+ Device (LPC) {
+ /* PCI D31:f0 */
+ Name (_ADR, 0x001f0000)
+
+ /* ICH9 PCI to ISA irq remapping */
+ OperationRegion (PIRQ, PCI_Config, 0x60, 0x0C)
+ Field (PIRQ, ByteAcc, NoLock, Preserve)
+ {
+ PRQA, 8,
+ PRQB, 8,
+ PRQC, 8,
+ PRQD, 8,
+
+ Offset (0x08),
+ PRQE, 8,
+ PRQF, 8,
+ PRQG, 8,
+ PRQH, 8
+ }
+
+ OperationRegion (LPCD, PCI_Config, 0x80, 0x2)
+ Field (LPCD, AnyAcc, NoLock, Preserve)
+ {
+ COMA, 3,
+ , 1,
+ COMB, 3,
+
+ Offset(0x01),
+ LPTD, 2,
+ , 2,
+ FDCD, 2
+ }
+ OperationRegion (LPCE, PCI_Config, 0x82, 0x2)
+ Field (LPCE, AnyAcc, NoLock, Preserve)
+ {
+ CAEN, 1,
+ CBEN, 1,
+ LPEN, 1,
+ FDEN, 1
+ }
+ /* High Precision Event Timer */
+ Device(HPET) {
+ Name(_HID, EISAID("PNP0103"))
+ Name(_UID, 0)
+ Method (_STA, 0, NotSerialized) {
+ Return(0x0F)
+ }
+ Name(_CRS, ResourceTemplate() {
+ DWordMemory(
+ ResourceConsumer, PosDecode, MinFixed, MaxFixed,
+ NonCacheable, ReadWrite,
+ 0x00000000,
+ 0xFED00000,
+ 0xFED003FF,
+ 0x00000000,
+ 0x00000400 /* 1K memory: FED00000 - FED003FF */
+ )
+ })
+ }
/* Real-time clock */
Device (RTC)
{
@@ -306,7 +377,15 @@ DefinitionBlock (
Name (_HID, EisaId ("PNP0700"))
Method (_STA, 0, NotSerialized)
{
- Return (0x0F)
+ Store (\_SB.PCI0.LPC.FDEN, Local0)
+ If (LEqual (Local0, 0))
+ {
+ Return (0x00)
+ }
+ Else
+ {
+ Return (0x0F)
+ }
}
Method (_CRS, 0, NotSerialized)
{
@@ -327,8 +406,7 @@ DefinitionBlock (
Name (_HID, EisaId ("PNP0400"))
Method (_STA, 0, NotSerialized)
{
- Store (\_SB.PCI0.PX13.DRSA, Local0)
- And (Local0, 0x80000000, Local0)
+ Store (\_SB.PCI0.LPC.LPEN, Local0)
If (LEqual (Local0, 0))
{
Return (0x00)
@@ -356,8 +434,7 @@ DefinitionBlock (
Name (_UID, 0x01)
Method (_STA, 0, NotSerialized)
{
- Store (\_SB.PCI0.PX13.DRSC, Local0)
- And (Local0, 0x08000000, Local0)
+ Store (\_SB.PCI0.LPC.CAEN, Local0)
If (LEqual (Local0, 0))
{
Return (0x00)
@@ -384,8 +461,7 @@ DefinitionBlock (
Name (_UID, 0x02)
Method (_STA, 0, NotSerialized)
{
- Store (\_SB.PCI0.PX13.DRSC, Local0)
- And (Local0, 0x80000000, Local0)
+ Store (\_SB.PCI0.LPC.CBEN, Local0)
If (LEqual (Local0, 0))
{
Return (0x00)
@@ -406,217 +482,88 @@ DefinitionBlock (
}
}
}
+ }
- /* PIIX4 PM */
- Device (PX13) {
- Name (_ADR, 0x00010003)
+ /* PCI to PCI Bridge on bus 0*/
+ Scope (\_SB.PCI0) {
+ Device (PCI6) {
+ Name (_ADR, 0x1e0000) /* 0:1e.00 */
+ Name (_UID, 6)
+ Name (_PRT, Package() {
+ prt_slots(A, B, C, D)
+ })
+ hotplug_slots(6)
+ }
+ }
- OperationRegion (P13C, PCI_Config, 0x5c, 0x24)
- Field (P13C, DWordAcc, NoLock, Preserve)
- {
- DRSA, 32,
- DRSB, 32,
- DRSC, 32,
- DRSE, 32,
- DRSF, 32,
- DRSG, 32,
- DRSH, 32,
- DRSI, 32,
- DRSJ, 32
- }
- }
+#define pci_bridge(dev, uid, bus, w, x, y, z) \
+ Scope (\_SB.PCI0.PCI6) { \
+ Device (PCI##uid) { \
+ Name (_ADR, 0x##dev##0000) \
+ Name (_UID, uid) \
+ Name (_PRT, Package() { \
+ prt_slots(w, x, y, z) \
+ }) \
+ hotplug_slots(bus) \
+ } \
}
+ pci_bridge(1d, 0, 7, A, B, C, D)
+ pci_bridge(1e, 1, 8, B, C, D, A)
+ pci_bridge(1f, 2, 9, C, D, A, B)
+
/* PCI IRQs */
Scope(\_SB) {
- Field (\_SB.PCI0.ISA.P40C, ByteAcc, NoLock, Preserve)
- {
- PRQ0, 8,
- PRQ1, 8,
- PRQ2, 8,
- PRQ3, 8
- }
-
- Device(LNKA){
- Name(_HID, EISAID("PNP0C0F")) // PCI interrupt link
- Name(_UID, 1)
- Name(_PRS, ResourceTemplate(){
- Interrupt (, Level, ActiveHigh, Shared)
- { 5, 10, 11 }
- })
- Method (_STA, 0, NotSerialized)
- {
- Store (0x0B, Local0)
- If (And (0x80, PRQ0, Local1))
- {
- Store (0x09, Local0)
- }
- Return (Local0)
- }
- Method (_DIS, 0, NotSerialized)
- {
- Or (PRQ0, 0x80, PRQ0)
- }
- Method (_CRS, 0, NotSerialized)
- {
- Name (PRR0, ResourceTemplate ()
- {
- Interrupt (, Level, ActiveHigh, Shared)
- {1}
- })
- CreateDWordField (PRR0, 0x05, TMP)
- Store (PRQ0, Local0)
- If (LLess (Local0, 0x80))
- {
- Store (Local0, TMP)
- }
- Else
- {
- Store (Zero, TMP)
- }
- Return (PRR0)
- }
- Method (_SRS, 1, NotSerialized)
- {
- CreateDWordField (Arg0, 0x05, TMP)
- Store (TMP, PRQ0)
- }
- }
- Device(LNKB){
- Name(_HID, EISAID("PNP0C0F")) // PCI interrupt link
- Name(_UID, 2)
- Name(_PRS, ResourceTemplate(){
- Interrupt (, Level, ActiveHigh, Shared)
- { 5, 10, 11 }
- })
- Method (_STA, 0, NotSerialized)
- {
- Store (0x0B, Local0)
- If (And (0x80, PRQ1, Local1))
- {
- Store (0x09, Local0)
- }
- Return (Local0)
- }
- Method (_DIS, 0, NotSerialized)
- {
- Or (PRQ1, 0x80, PRQ1)
- }
- Method (_CRS, 0, NotSerialized)
- {
- Name (PRR0, ResourceTemplate ()
- {
- Interrupt (, Level, ActiveHigh, Shared)
- {1}
- })
- CreateDWordField (PRR0, 0x05, TMP)
- Store (PRQ1, Local0)
- If (LLess (Local0, 0x80))
- {
- Store (Local0, TMP)
- }
- Else
- {
- Store (Zero, TMP)
- }
- Return (PRR0)
- }
- Method (_SRS, 1, NotSerialized)
- {
- CreateDWordField (Arg0, 0x05, TMP)
- Store (TMP, PRQ1)
- }
- }
- Device(LNKC){
- Name(_HID, EISAID("PNP0C0F")) // PCI interrupt link
- Name(_UID, 3)
- Name(_PRS, ResourceTemplate(){
- Interrupt (, Level, ActiveHigh, Shared)
- { 5, 10, 11 }
- })
- Method (_STA, 0, NotSerialized)
- {
- Store (0x0B, Local0)
- If (And (0x80, PRQ2, Local1))
- {
- Store (0x09, Local0)
- }
- Return (Local0)
- }
- Method (_DIS, 0, NotSerialized)
- {
- Or (PRQ2, 0x80, PRQ2)
- }
- Method (_CRS, 0, NotSerialized)
- {
- Name (PRR0, ResourceTemplate ()
- {
- Interrupt (, Level, ActiveHigh, Shared)
- {1}
- })
- CreateDWordField (PRR0, 0x05, TMP)
- Store (PRQ2, Local0)
- If (LLess (Local0, 0x80))
- {
- Store (Local0, TMP)
- }
- Else
- {
- Store (Zero, TMP)
- }
- Return (PRR0)
- }
- Method (_SRS, 1, NotSerialized)
- {
- CreateDWordField (Arg0, 0x05, TMP)
- Store (TMP, PRQ2)
- }
- }
- Device(LNKD){
- Name(_HID, EISAID("PNP0C0F")) // PCI interrupt link
- Name(_UID, 4)
- Name(_PRS, ResourceTemplate(){
- Interrupt (, Level, ActiveHigh, Shared)
- { 5, 10, 11 }
- })
- Method (_STA, 0, NotSerialized)
- {
- Store (0x0B, Local0)
- If (And (0x80, PRQ3, Local1))
- {
- Store (0x09, Local0)
- }
- Return (Local0)
- }
- Method (_DIS, 0, NotSerialized)
- {
- Or (PRQ3, 0x80, PRQ3)
- }
- Method (_CRS, 0, NotSerialized)
- {
- Name (PRR0, ResourceTemplate ()
- {
- Interrupt (, Level, ActiveHigh, Shared)
- {1}
- })
- CreateDWordField (PRR0, 0x05, TMP)
- Store (PRQ3, Local0)
- If (LLess (Local0, 0x80))
- {
- Store (Local0, TMP)
- }
- Else
- {
- Store (Zero, TMP)
- }
- Return (PRR0)
- }
- Method (_SRS, 1, NotSerialized)
- {
- CreateDWordField (Arg0, 0x05, TMP)
- Store (TMP, PRQ3)
- }
+#define define_link(link, uid, reg) \
+ Device(link){ \
+ Name(_HID, EISAID("PNP0C0F")) \
+ Name(_UID, uid) \
+ Name(_PRS, ResourceTemplate(){ \
+ Interrupt (, Level, ActiveHigh, \
+ Shared) \
+ { 5, 10, 11 } \
+ }) \
+ Method (_STA, 0, NotSerialized) \
+ { \
+ Store (0x0B, Local0) \
+ If (And (0x80, reg, Local1)) \
+ { \
+ Store (0x09, Local0) \
+ } \
+ Return (Local0) \
+ } \
+ Method (_DIS, 0, NotSerialized) \
+ { \
+ Or (reg, 0x80, reg) \
+ } \
+ Method (_CRS, 0, NotSerialized) \
+ { \
+ Name (PRR0, ResourceTemplate () \
+ { \
+ Interrupt (, Level, ActiveHigh, \
+ Shared) \
+ {1} \
+ }) \
+ CreateDWordField (PRR0, 0x05, TMP) \
+ And (reg, 0x0F, Local0) \
+ Store (Local0, TMP) \
+ Return (PRR0) \
+ } \
+ Method (_SRS, 1, NotSerialized) \
+ { \
+ CreateDWordField (Arg0, 0x05, TMP) \
+ Store (TMP, reg) \
+ } \
}
+
+ define_link(LNKA, 0, \_SB.PCI0.LPC.PRQA)
+ define_link(LNKB, 1, \_SB.PCI0.LPC.PRQB)
+ define_link(LNKC, 2, \_SB.PCI0.LPC.PRQC)
+ define_link(LNKD, 3, \_SB.PCI0.LPC.PRQD)
+ define_link(LNKE, 4, \_SB.PCI0.LPC.PRQE)
+ define_link(LNKF, 5, \_SB.PCI0.LPC.PRQF)
+ define_link(LNKG, 6, \_SB.PCI0.LPC.PRQG)
+ define_link(LNKH, 7, \_SB.PCI0.LPC.PRQH)
}
/*
@@ -653,46 +600,62 @@ DefinitionBlock (
Return(0x01)
}
-#define gen_pci_hotplug(nr) \
- If (And(\_SB.PCI0.PCIU, ShiftLeft(1, nr))) { \
- Notify(\_SB.PCI0.S##nr, 1) \
+#define gen_pci_hotplug(nr, DEV) \
+ If (And(\_SB.PCIU, ShiftLeft(1, nr))) { \
+ Notify(DEV##.S##nr, 1) \
} \
- If (And(\_SB.PCI0.PCID, ShiftLeft(1, nr))) { \
- Notify(\_SB.PCI0.S##nr, 3) \
+ If (And(\_SB.PCID, ShiftLeft(1, nr))) { \
+ Notify(DEV##.S##nr, 3) \
}
+#define gen_pci_hotplug_1(DEV) \
+ gen_pci_hotplug(1, DEV) \
+ gen_pci_hotplug(2, DEV) \
+ gen_pci_hotplug(3, DEV) \
+ gen_pci_hotplug(4, DEV) \
+ gen_pci_hotplug(5, DEV) \
+ gen_pci_hotplug(6, DEV) \
+ gen_pci_hotplug(7, DEV) \
+ gen_pci_hotplug(8, DEV) \
+ gen_pci_hotplug(9, DEV) \
+ gen_pci_hotplug(10, DEV) \
+ gen_pci_hotplug(11, DEV) \
+ gen_pci_hotplug(12, DEV) \
+ gen_pci_hotplug(13, DEV) \
+ gen_pci_hotplug(14, DEV) \
+ gen_pci_hotplug(15, DEV) \
+ gen_pci_hotplug(16, DEV) \
+ gen_pci_hotplug(17, DEV) \
+ gen_pci_hotplug(18, DEV) \
+ gen_pci_hotplug(19, DEV) \
+ gen_pci_hotplug(20, DEV) \
+ gen_pci_hotplug(21, DEV) \
+ gen_pci_hotplug(22, DEV) \
+ gen_pci_hotplug(23, DEV) \
+ gen_pci_hotplug(24, DEV) \
+ gen_pci_hotplug(25, DEV) \
+ gen_pci_hotplug(26, DEV) \
+ gen_pci_hotplug(27, DEV) \
+ gen_pci_hotplug(28, DEV) \
+ gen_pci_hotplug(29, DEV) \
+ gen_pci_hotplug(30, DEV) \
+ gen_pci_hotplug(31, DEV)
+
+#define gen_pci_hotplugs1(DEV, bus) \
+ Store(bus, \_SB.PCIB) \
+ gen_pci_hotplug_1(DEV)
+
+#define gen_pci_hotplugs(DEV, bus) \
+ Store(bus, \_SB.PCIB) \
+ gen_pci_hotplug(0, DEV) \
+ gen_pci_hotplug_1(DEV)
+
Method(_L01) {
- gen_pci_hotplug(1)
- gen_pci_hotplug(2)
- gen_pci_hotplug(3)
- gen_pci_hotplug(4)
- gen_pci_hotplug(5)
- gen_pci_hotplug(6)
- gen_pci_hotplug(7)
- gen_pci_hotplug(8)
- gen_pci_hotplug(9)
- gen_pci_hotplug(10)
- gen_pci_hotplug(11)
- gen_pci_hotplug(12)
- gen_pci_hotplug(13)
- gen_pci_hotplug(14)
- gen_pci_hotplug(15)
- gen_pci_hotplug(16)
- gen_pci_hotplug(17)
- gen_pci_hotplug(18)
- gen_pci_hotplug(19)
- gen_pci_hotplug(20)
- gen_pci_hotplug(21)
- gen_pci_hotplug(22)
- gen_pci_hotplug(23)
- gen_pci_hotplug(24)
- gen_pci_hotplug(25)
- gen_pci_hotplug(26)
- gen_pci_hotplug(27)
- gen_pci_hotplug(28)
- gen_pci_hotplug(29)
- gen_pci_hotplug(30)
- gen_pci_hotplug(31)
+ gen_pci_hotplugs1(\_SB.PCI0, 0)
+ gen_pci_hotplugs(\_SB.PCI0.PCI6, 6)
+ gen_pci_hotplugs(\_SB.PCI0.PCI6.PCI0, 7)
+ gen_pci_hotplugs(\_SB.PCI0.PCI6.PCI1, 8)
+ gen_pci_hotplugs(\_SB.PCI0.PCI6.PCI2, 9)
Return (0x01)
--
1.6.0.2
^ permalink raw reply related [flat|nested] 20+ messages in thread* [Qemu-devel] [PATCH 14/14] pcibos/acpi dsdt: APIC mode support for q35 chipset
2009-09-30 10:18 [Qemu-devel] [PATCH 00/14] pcbios: support q35 chipset Isaku Yamahata
` (12 preceding siblings ...)
2009-09-30 10:18 ` [Qemu-devel] [PATCH 13/14] pcbios: change acpi dsdt for q35 chipset Isaku Yamahata
@ 2009-09-30 10:18 ` Isaku Yamahata
2009-09-30 13:23 ` [Qemu-devel] Re: [PATCH 00/14] pcbios: support " Anthony Liguori
14 siblings, 0 replies; 20+ messages in thread
From: Isaku Yamahata @ 2009-09-30 10:18 UTC (permalink / raw)
To: qemu-devel, anthony; +Cc: yamahata
APIC mode support for q35 chipset.
Currently gsi 16-19 are used.
Signed-off-by: Isaku Yamahata <yamahata@valinux.co.jp>
---
acpi-dsdt.dsl | 181 +++++++++++++++++++++++++++++++++++++++++----------------
1 files changed, 130 insertions(+), 51 deletions(-)
diff --git a/acpi-dsdt.dsl b/acpi-dsdt.dsl
index d75927b..19743bc 100644
--- a/acpi-dsdt.dsl
+++ b/acpi-dsdt.dsl
@@ -72,65 +72,142 @@ DefinitionBlock (
}
}
+ /* Zero => PIC mode, One => APIC Mode */
+ Name (\PICF, Zero)
+ Method (\_PIC, 1, NotSerialized)
+ {
+ Store (Arg0, \PICF)
+ }
+
/* PCI Bus definition */
Scope(\_SB) {
+
Device(PCI0) {
Name (_HID, EisaId ("PNP0A08"))
Name (_CID, EisaId ("PNP0A03"))
Name (_ADR, 0x00)
Name (_UID, 1)
- Name(_PRT, Package() {
+
+#define prt_slot_lnk(nr, lnk0, lnk1, lnk2, lnk3) \
+ Package() { nr##ffff, 0, lnk0, 0 }, \
+ Package() { nr##ffff, 1, lnk1, 0 }, \
+ Package() { nr##ffff, 2, lnk2, 0 }, \
+ Package() { nr##ffff, 3, lnk3, 0 }
+
+#define prt_slot_lnkD(nr) prt_slot_lnk(nr, LNKD, LNKA, LNKB, LNKC)
+#define prt_slot_lnkA(nr) prt_slot_lnk(nr, LNKA, LNKB, LNKC, LNKD)
+#define prt_slot_lnkB(nr) prt_slot_lnk(nr, LNKB, LNKC, LNKD, LNKA)
+#define prt_slot_lnkC(nr) prt_slot_lnk(nr, LNKC, LNKD, LNKA, LNKB)
+
+#define prt_slot_lnk_all(w, x, y, z) \
+ prt_slot_lnk##w(0x0000), \
+ prt_slot_lnk##x(0x0001), \
+ prt_slot_lnk##y(0x0002), \
+ prt_slot_lnk##z(0x0003), \
+ prt_slot_lnk##w(0x0004), \
+ prt_slot_lnk##x(0x0005), \
+ prt_slot_lnk##y(0x0006), \
+ prt_slot_lnk##z(0x0007), \
+ prt_slot_lnk##w(0x0008), \
+ prt_slot_lnk##x(0x0009), \
+ prt_slot_lnk##y(0x000a), \
+ prt_slot_lnk##z(0x000b), \
+ prt_slot_lnk##w(0x000c), \
+ prt_slot_lnk##x(0x000d), \
+ prt_slot_lnk##y(0x000e), \
+ prt_slot_lnk##z(0x000f), \
+ prt_slot_lnk##w(0x0010), \
+ prt_slot_lnk##x(0x0011), \
+ prt_slot_lnk##y(0x0012), \
+ prt_slot_lnk##z(0x0013), \
+ prt_slot_lnk##w(0x0014), \
+ prt_slot_lnk##x(0x0015), \
+ prt_slot_lnk##y(0x0016), \
+ prt_slot_lnk##z(0x0017), \
+ prt_slot_lnk##w(0x0018), \
+ prt_slot_lnk##x(0x0019), \
+ prt_slot_lnk##y(0x001a), \
+ prt_slot_lnk##z(0x001b), \
+ prt_slot_lnk##w(0x001c), \
+ prt_slot_lnk##x(0x001d), \
+ prt_slot_lnk##y(0x001e), \
+ prt_slot_lnk##z(0x001f), \
+
+#define prt_slot_gsi(nr, gsi0, gsi1, gsi2, gsi3) \
+ Package() { nr##ffff, 0, 0, gsi0 }, \
+ Package() { nr##ffff, 1, 0, gsi1 }, \
+ Package() { nr##ffff, 2, 0, gsi2 }, \
+ Package() { nr##ffff, 3, 0, gsi3 }
+
+#define GSIA 0x10
+#define GSIB 0x11
+#define GSIC 0x12
+#define GSID 0x13
+#define GSIE 0x14
+#define GSIF 0x15
+#define GSIG 0x16
+#define GSIH 0x17
+
+#define prt_slot_gsiD(nr) prt_slot_gsi(nr, GSID, GSIA, GSIB, GSIC)
+#define prt_slot_gsiA(nr) prt_slot_gsi(nr, GSIA, GSIB, GSIC, GSID)
+#define prt_slot_gsiB(nr) prt_slot_gsi(nr, GSIB, GSIC, GSID, GSIA)
+#define prt_slot_gsiC(nr) prt_slot_gsi(nr, GSIC, GSID, GSIA, GSIB)
+
+#define prt_slot_gsi_all(w, x, y, z) \
+ prt_slot_gsi##w(0x0000), \
+ prt_slot_gsi##x(0x0001), \
+ prt_slot_gsi##y(0x0002), \
+ prt_slot_gsi##z(0x0003), \
+ prt_slot_gsi##w(0x0004), \
+ prt_slot_gsi##x(0x0005), \
+ prt_slot_gsi##y(0x0006), \
+ prt_slot_gsi##z(0x0007), \
+ prt_slot_gsi##w(0x0008), \
+ prt_slot_gsi##x(0x0009), \
+ prt_slot_gsi##y(0x000a), \
+ prt_slot_gsi##z(0x000b), \
+ prt_slot_gsi##w(0x000c), \
+ prt_slot_gsi##x(0x000d), \
+ prt_slot_gsi##y(0x000e), \
+ prt_slot_gsi##z(0x000f), \
+ prt_slot_gsi##w(0x0010), \
+ prt_slot_gsi##x(0x0011), \
+ prt_slot_gsi##y(0x0012), \
+ prt_slot_gsi##z(0x0013), \
+ prt_slot_gsi##w(0x0014), \
+ prt_slot_gsi##x(0x0015), \
+ prt_slot_gsi##y(0x0016), \
+ prt_slot_gsi##z(0x0017), \
+ prt_slot_gsi##w(0x0018), \
+ prt_slot_gsi##x(0x0019), \
+ prt_slot_gsi##y(0x001a), \
+ prt_slot_gsi##z(0x001b), \
+ prt_slot_gsi##w(0x001c), \
+ prt_slot_gsi##x(0x001d), \
+ prt_slot_gsi##y(0x001e), \
+ prt_slot_gsi##z(0x001f), \
+
+#define prt_slots(w, x, y, z) \
+ If (LEqual (\PICF, Zero)) \
+ { \
+ Return (Package() { \
+ prt_slot_lnk_all(w, x, y, z) \
+ }) \
+ } \
+ Else \
+ { \
+ Return (Package() { \
+ prt_slot_gsi_all(w, x, y, z) \
+ }) \
+ }
+ Method(_PRT, 0, NotSerialized)
+ {
/* PCI IRQ routing table, example from ACPI 2.0a specification,
section 6.2.8.1 */
/* Note: we provide the same info as the PCI routing
table of the Bochs BIOS */
-#define prt_slot(nr, lnk0, lnk1, lnk2, lnk3) \
- Package() { nr##ffff, 0, lnk0, 0 }, \
- Package() { nr##ffff, 1, lnk1, 0 }, \
- Package() { nr##ffff, 2, lnk2, 0 }, \
- Package() { nr##ffff, 3, lnk3, 0 }
-
-#define prt_slotD(nr) prt_slot(nr, LNKD, LNKA, LNKB, LNKC)
-#define prt_slotA(nr) prt_slot(nr, LNKA, LNKB, LNKC, LNKD)
-#define prt_slotB(nr) prt_slot(nr, LNKB, LNKC, LNKD, LNKA)
-#define prt_slotC(nr) prt_slot(nr, LNKC, LNKD, LNKA, LNKB)
-
-#define prt_slots(w, x, y, z) \
- prt_slot##w(0x0000), \
- prt_slot##x(0x0001), \
- prt_slot##y(0x0002), \
- prt_slot##z(0x0003), \
- prt_slot##w(0x0004), \
- prt_slot##x(0x0005), \
- prt_slot##y(0x0006), \
- prt_slot##z(0x0007), \
- prt_slot##w(0x0008), \
- prt_slot##x(0x0009), \
- prt_slot##y(0x000a), \
- prt_slot##z(0x000b), \
- prt_slot##w(0x000c), \
- prt_slot##x(0x000d), \
- prt_slot##y(0x000e), \
- prt_slot##z(0x000f), \
- prt_slot##w(0x0010), \
- prt_slot##x(0x0011), \
- prt_slot##y(0x0012), \
- prt_slot##z(0x0013), \
- prt_slot##w(0x0014), \
- prt_slot##x(0x0015), \
- prt_slot##y(0x0016), \
- prt_slot##z(0x0017), \
- prt_slot##w(0x0018), \
- prt_slot##x(0x0019), \
- prt_slot##y(0x001a), \
- prt_slot##z(0x001b), \
- prt_slot##w(0x001c), \
- prt_slot##x(0x001d), \
- prt_slot##y(0x001e), \
- prt_slot##z(0x001f),
-
prt_slots(D, A, B, C)
- })
+ }
#define hotplug_slot(name, nr, bus) \
Device (S##name) { \
@@ -489,9 +566,10 @@ DefinitionBlock (
Device (PCI6) {
Name (_ADR, 0x1e0000) /* 0:1e.00 */
Name (_UID, 6)
- Name (_PRT, Package() {
+ Method(_PRT, 0, NotSerialized)
+ {
prt_slots(A, B, C, D)
- })
+ }
hotplug_slots(6)
}
}
@@ -501,9 +579,10 @@ DefinitionBlock (
Device (PCI##uid) { \
Name (_ADR, 0x##dev##0000) \
Name (_UID, uid) \
- Name (_PRT, Package() { \
+ Method(_PRT, 0, NotSerialized) \
+ { \
prt_slots(w, x, y, z) \
- }) \
+ } \
hotplug_slots(bus) \
} \
}
--
1.6.0.2
^ permalink raw reply related [flat|nested] 20+ messages in thread* [Qemu-devel] Re: [PATCH 00/14] pcbios: support q35 chipset
2009-09-30 10:18 [Qemu-devel] [PATCH 00/14] pcbios: support q35 chipset Isaku Yamahata
` (13 preceding siblings ...)
2009-09-30 10:18 ` [Qemu-devel] [PATCH 14/14] pcibos/acpi dsdt: APIC mode support " Isaku Yamahata
@ 2009-09-30 13:23 ` Anthony Liguori
2009-09-30 16:14 ` Gleb Natapov
2009-10-01 5:49 ` Isaku Yamahata
14 siblings, 2 replies; 20+ messages in thread
From: Anthony Liguori @ 2009-09-30 13:23 UTC (permalink / raw)
To: Isaku Yamahata; +Cc: qemu-devel
Isaku Yamahata wrote:
> This patches to pcbios is for q35 chipset.
> This is The change set of da5ff65dc9473e3f069736d38b9a189ea14a67eb
> in git://git.qemu.org/pcbios.git
>
Patches against SeaBIOS are also required as we're planning to switch to
SeaBIOS.
In fact, you don't need to bother with pcbios if you'd rather focus on
SeaBIOS.
> There would be a discussion to change bioses.
> This patches modifies ACPI DSDT directly which
> is linked into bios binary image.
> This would not be acceptable and it would be a bad
> idea to have two bios binary image for piix and q35.
> So instead, I'm thinking of dynamic loading ACPI table.
> I'd like to hear opinions. What do you think?
>
Could we dynamically generate the necessary tables? Using iasl is a bit
problematic as we introduce more knobs via qdev. I expect that we're
going to move to an almost entirely generated set of tables.
Regards,
Anthony Liguori
^ permalink raw reply [flat|nested] 20+ messages in thread* Re: [Qemu-devel] Re: [PATCH 00/14] pcbios: support q35 chipset
2009-09-30 13:23 ` [Qemu-devel] Re: [PATCH 00/14] pcbios: support " Anthony Liguori
@ 2009-09-30 16:14 ` Gleb Natapov
2009-10-01 5:49 ` Isaku Yamahata
1 sibling, 0 replies; 20+ messages in thread
From: Gleb Natapov @ 2009-09-30 16:14 UTC (permalink / raw)
To: Anthony Liguori; +Cc: Isaku Yamahata, qemu-devel
On Wed, Sep 30, 2009 at 08:23:59AM -0500, Anthony Liguori wrote:
> Isaku Yamahata wrote:
> >This patches to pcbios is for q35 chipset.
> >This is The change set of da5ff65dc9473e3f069736d38b9a189ea14a67eb
> >in git://git.qemu.org/pcbios.git
>
> Patches against SeaBIOS are also required as we're planning to
> switch to SeaBIOS.
>
> In fact, you don't need to bother with pcbios if you'd rather focus
> on SeaBIOS.
>
> >There would be a discussion to change bioses.
> >This patches modifies ACPI DSDT directly which
> >is linked into bios binary image.
> >This would not be acceptable and it would be a bad
> >idea to have two bios binary image for piix and q35.
> >So instead, I'm thinking of dynamic loading ACPI table.
> >I'd like to hear opinions. What do you think?
>
> Could we dynamically generate the necessary tables? Using iasl is a
> bit problematic as we introduce more knobs via qdev. I expect that
> we're going to move to an almost entirely generated set of tables.
>
Is is almost impossible to dynamically generate DSDT that does
nontrivial things. We can use different SSDT for different chipset
and decide which one to use in runtime.
--
Gleb.
^ permalink raw reply [flat|nested] 20+ messages in thread
* [Qemu-devel] Re: [PATCH 00/14] pcbios: support q35 chipset
2009-09-30 13:23 ` [Qemu-devel] Re: [PATCH 00/14] pcbios: support " Anthony Liguori
2009-09-30 16:14 ` Gleb Natapov
@ 2009-10-01 5:49 ` Isaku Yamahata
2009-10-01 8:01 ` Carl-Daniel Hailfinger
2009-10-01 14:46 ` Gleb Natapov
1 sibling, 2 replies; 20+ messages in thread
From: Isaku Yamahata @ 2009-10-01 5:49 UTC (permalink / raw)
To: Anthony Liguori; +Cc: qemu-devel
On Wed, Sep 30, 2009 at 08:23:59AM -0500, Anthony Liguori wrote:
> Isaku Yamahata wrote:
> >This patches to pcbios is for q35 chipset.
> >This is The change set of da5ff65dc9473e3f069736d38b9a189ea14a67eb
> >in git://git.qemu.org/pcbios.git
> >
>
> Patches against SeaBIOS are also required as we're planning to switch to
> SeaBIOS.
>
> In fact, you don't need to bother with pcbios if you'd rather focus on
> SeaBIOS.
I see. Do you have schedule plan of the switch in mind?
> >There would be a discussion to change bioses.
> >This patches modifies ACPI DSDT directly which
> >is linked into bios binary image.
> >This would not be acceptable and it would be a bad
> >idea to have two bios binary image for piix and q35.
> >So instead, I'm thinking of dynamic loading ACPI table.
> >I'd like to hear opinions. What do you think?
> >
>
> Could we dynamically generate the necessary tables? Using iasl is a bit
> problematic as we introduce more knobs via qdev. I expect that we're
> going to move to an almost entirely generated set of tables.
So at least an interface to pass acpi tables to guest bios from qemu
is necessary. FW_CFG interface seems reasonable.
Generating tables dynamically sounds attractive. However it seems much
longer term goal like machine config file.
--
yamahata
^ permalink raw reply [flat|nested] 20+ messages in thread
* Re: [Qemu-devel] Re: [PATCH 00/14] pcbios: support q35 chipset
2009-10-01 5:49 ` Isaku Yamahata
@ 2009-10-01 8:01 ` Carl-Daniel Hailfinger
2009-10-01 14:46 ` Gleb Natapov
1 sibling, 0 replies; 20+ messages in thread
From: Carl-Daniel Hailfinger @ 2009-10-01 8:01 UTC (permalink / raw)
To: Isaku Yamahata; +Cc: qemu-devel
On 01.10.2009 07:49, Isaku Yamahata wrote:
> On Wed, Sep 30, 2009 at 08:23:59AM -0500, Anthony Liguori wrote:
>
>> Could we dynamically generate the necessary tables? Using iasl is a bit
>> problematic as we introduce more knobs via qdev. I expect that we're
>> going to move to an almost entirely generated set of tables.
>>
>
> So at least an interface to pass acpi tables to guest bios from qemu
> is necessary. FW_CFG interface seems reasonable.
> Generating tables dynamically sounds attractive. However it seems much
> longer term goal like machine config file.
>
I think coreboot has code to dynamically generate ACPI tables. Patching
precompiled ACPI tables was a major source of pain for coreboot
developers in the past, so we switched to generating the dynamic tables
from scratch during runtime.
Regards,
Carl-Daniel
--
http://www.hailfinger.org/
^ permalink raw reply [flat|nested] 20+ messages in thread
* Re: [Qemu-devel] Re: [PATCH 00/14] pcbios: support q35 chipset
2009-10-01 5:49 ` Isaku Yamahata
2009-10-01 8:01 ` Carl-Daniel Hailfinger
@ 2009-10-01 14:46 ` Gleb Natapov
1 sibling, 0 replies; 20+ messages in thread
From: Gleb Natapov @ 2009-10-01 14:46 UTC (permalink / raw)
To: Isaku Yamahata; +Cc: qemu-devel
On Thu, Oct 01, 2009 at 02:49:03PM +0900, Isaku Yamahata wrote:
> > >There would be a discussion to change bioses.
> > >This patches modifies ACPI DSDT directly which
> > >is linked into bios binary image.
> > >This would not be acceptable and it would be a bad
> > >idea to have two bios binary image for piix and q35.
> > >So instead, I'm thinking of dynamic loading ACPI table.
> > >I'd like to hear opinions. What do you think?
> > >
> >
> > Could we dynamically generate the necessary tables? Using iasl is a bit
> > problematic as we introduce more knobs via qdev. I expect that we're
> > going to move to an almost entirely generated set of tables.
>
> So at least an interface to pass acpi tables to guest bios from qemu
> is necessary. FW_CFG interface seems reasonable.
> Generating tables dynamically sounds attractive. However it seems much
> longer term goal like machine config file.
We already have interface to pass acpi tables to bios, but tables like
DSDT should be part of the bios, not qemu.
--
Gleb.
^ permalink raw reply [flat|nested] 20+ messages in thread