From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mailman by lists.gnu.org with tmda-scanned (Exim 4.43) id 1MtO95-0003dS-Qp for qemu-devel@nongnu.org; Thu, 01 Oct 2009 12:04:43 -0400 Received: from exim by lists.gnu.org with spam-scanned (Exim 4.43) id 1MtO91-0003Xb-78 for qemu-devel@nongnu.org; Thu, 01 Oct 2009 12:04:43 -0400 Received: from [199.232.76.173] (port=34095 helo=monty-python.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1MtO90-0003XF-Tf for qemu-devel@nongnu.org; Thu, 01 Oct 2009 12:04:39 -0400 Received: from mx1.redhat.com ([209.132.183.28]:52863) by monty-python.gnu.org with esmtp (Exim 4.60) (envelope-from ) id 1MtO90-0005NP-5N for qemu-devel@nongnu.org; Thu, 01 Oct 2009 12:04:38 -0400 Message-ID: <4AC4D30E.1050500@redhat.com> Date: Thu, 01 Oct 2009 18:04:30 +0200 From: Avi Kivity MIME-Version: 1.0 Subject: Re: [Qemu-devel] [PATCH 57/61] ioapic: add callback when entry is set or ioapic is reset References: <1254305917-14784-1-git-send-email-yamahata@valinux.co.jp> <1254305917-14784-58-git-send-email-yamahata@valinux.co.jp> <20091001133716.GT9832@redhat.com> In-Reply-To: <20091001133716.GT9832@redhat.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Gleb Natapov Cc: Isaku Yamahata , qemu-devel@nongnu.org On 10/01/2009 03:37 PM, Gleb Natapov wrote: > On Wed, Sep 30, 2009 at 07:18:33PM +0900, Isaku Yamahata wrote: > >> Add hooks to ioapic. >> This is necessary for pci interrupt routing mode from >> PIC mode to IO APIC mode. >> > According to my very brief looking at ICH9 spec switching from PIC mode > to IO APIC mode is done separately for each PIRQ by setting bit 7 of > PIRQ[n]_ROUT register to 1. This callback looks completely out of place. > Disassembling the _PIC and _PRT methods of a Q35 machine will probably yield how this is done on real hardware. -- Do not meddle in the internals of kernels, for they are subtle and quick to panic.