From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mailman by lists.gnu.org with tmda-scanned (Exim 4.43) id 1MxLvz-0006s8-8u for qemu-devel@nongnu.org; Mon, 12 Oct 2009 10:31:35 -0400 Received: from exim by lists.gnu.org with spam-scanned (Exim 4.43) id 1MxLvu-0006oc-Iv for qemu-devel@nongnu.org; Mon, 12 Oct 2009 10:31:34 -0400 Received: from [199.232.76.173] (port=55349 helo=monty-python.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1MxLvu-0006oO-8g for qemu-devel@nongnu.org; Mon, 12 Oct 2009 10:31:30 -0400 Received: from mail-fx0-f214.google.com ([209.85.220.214]:47152) by monty-python.gnu.org with esmtp (Exim 4.60) (envelope-from ) id 1MxLvt-0007ZY-Ti for qemu-devel@nongnu.org; Mon, 12 Oct 2009 10:31:30 -0400 Received: by fxm10 with SMTP id 10so8127939fxm.8 for ; Mon, 12 Oct 2009 07:31:29 -0700 (PDT) Message-ID: <4AD33DBA.5070106@codemonkey.ws> Date: Mon, 12 Oct 2009 09:31:22 -0500 From: Anthony Liguori MIME-Version: 1.0 Subject: Re: [Qemu-devel] Re: [PATCH 2/3] qemu: make cirrus init value pci spec compliant References: <20091008160623.GA13710@redhat.com> <4ACE0FC6.3050908@redhat.com> <20091008184011.GA6576@shareable.org> <20091011133626.GA10229@redhat.com> <20091011134559.GN16702@redhat.com> <20091011135240.GA10277@redhat.com> <20091011135748.GO16702@redhat.com> <20091011143535.GA10401@redhat.com> <20091011143946.GP16702@redhat.com> <4AD332D8.8080903@us.ibm.com> <20091012142129.GE3026@redhat.com> In-Reply-To: <20091012142129.GE3026@redhat.com> Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Gleb Natapov Cc: Anthony Liguori , "Michael S. Tsirkin" , "qemu-devel@nongnu.org" , kvm-devel , Avi Kivity Gleb Natapov wrote: > On Mon, Oct 12, 2009 at 08:44:56AM -0500, Anthony Liguori wrote: > >> Gleb Natapov wrote >> >>>> BTW, I don't think it's write-protected and it probably should be? >>>> >>>> >>> AFAIR it is not writable on plain qemu. >>> >> KVM wants it to be writable for the TPR optimization. Historically, >> > I don't think so. TPR will work after BIOS will be shadowed. This is simply > KVM shortcoming. > > >> it was read-only in QEMU but it changed to read-write in order to >> > I just checked. It is still read-only in QEMU _before_ BIOS is shadowed. > > >> fake coreboot into thinking that the bios implemented PMM which it >> doesn't. >> > What is PMM? Post memory manager? How is it related? > I was thinking of option rom memory. BIOS memory is still read-only. Regards, Anthony Liguori