From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mailman by lists.gnu.org with tmda-scanned (Exim 4.43) id 1N3TB4-0000Yj-R2 for qemu-devel@nongnu.org; Thu, 29 Oct 2009 07:28:26 -0400 Received: from exim by lists.gnu.org with spam-scanned (Exim 4.43) id 1N3TAz-0000Wi-RR for qemu-devel@nongnu.org; Thu, 29 Oct 2009 07:28:26 -0400 Received: from [199.232.76.173] (port=43045 helo=monty-python.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1N3TAz-0000Wc-9O for qemu-devel@nongnu.org; Thu, 29 Oct 2009 07:28:21 -0400 Received: from mail-ew0-f206.google.com ([209.85.219.206]:64623) by monty-python.gnu.org with esmtp (Exim 4.60) (envelope-from ) id 1N3TAy-0007bh-TW for qemu-devel@nongnu.org; Thu, 29 Oct 2009 07:28:21 -0400 Received: by ewy2 with SMTP id 2so1634719ewy.34 for ; Thu, 29 Oct 2009 04:28:19 -0700 (PDT) Message-ID: <4AE97CBA.80600@gmail.com> Date: Thu, 29 Oct 2009 12:30:02 +0100 From: =?UTF-8?B?TcOgcml1cyBNb250w7Nu?= MIME-Version: 1.0 Subject: Re: [Qemu-devel] Re: PCI address question References: <4ADED9A0.3000605@gmail.com> <4AE70C35.6050909@gmail.com> <20091027151640.GH5526@csclub.uwaterloo.ca> In-Reply-To: <20091027151640.GH5526@csclub.uwaterloo.ca> Content-Type: text/html; charset=UTF-8 Content-Transfer-Encoding: 8bit List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Lennart Sorensen wrote:

On Tue, Oct 27, 2009 at 04:05:25PM +0100, Màrius Montón wrote:

Màrius Montón wrote:

Hello,

For my PCI device to QEMU, I need the real address the PCI bus is using
to access my device. For a IO BAR (PCI_ADDRESS_SPACE_IO), I receive the
real address (like 0xc200 or similar), but when registering a
PCI_ADDRESS_SPACE_MEM I only receive the offset to the BAR.

How I can receive or obtaint the real address on each access to my device?

Cjeers,

Màrius

nobody can tell me anything? :(


Add the offset to the address in the bar?

The problem is how to know what bar is accessing in case I have only one function for all BARs.

After all the OS is allowed to change your BAR if it wants to.
So internally the only thing that makes sense to a PCI device is the
offset from it's base address.

You listen to addresses at your IO range, and at your memory BAR range.
What you do when you see a request for your range then depends on the
offset that address had from the current base.  This would also be true
for the IO.

I know all PCI internals, but I don't understand why for IO I receive all address and only the offset for MEM BARs (or I'm wrong?)

Màrius