From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mailman by lists.gnu.org with tmda-scanned (Exim 4.43) id 1NFk2k-0000Ag-Nx for qemu-devel@nongnu.org; Wed, 02 Dec 2009 02:54:34 -0500 Received: from exim by lists.gnu.org with spam-scanned (Exim 4.43) id 1NFk2f-0000A5-NS for qemu-devel@nongnu.org; Wed, 02 Dec 2009 02:54:33 -0500 Received: from [199.232.76.173] (port=36993 helo=monty-python.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1NFk2f-0000A2-JR for qemu-devel@nongnu.org; Wed, 02 Dec 2009 02:54:29 -0500 Received: from mx20.gnu.org ([199.232.41.8]:34860) by monty-python.gnu.org with esmtps (TLS-1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.60) (envelope-from ) id 1NFk2f-0007FI-2F for qemu-devel@nongnu.org; Wed, 02 Dec 2009 02:54:29 -0500 Received: from mtagate5.de.ibm.com ([195.212.17.165]) by mx20.gnu.org with esmtp (Exim 4.60) (envelope-from ) id 1NFk2b-0003ki-D6 for qemu-devel@nongnu.org; Wed, 02 Dec 2009 02:54:25 -0500 Received: from d12nrmr1607.megacenter.de.ibm.com (d12nrmr1607.megacenter.de.ibm.com [9.149.167.49]) by mtagate5.de.ibm.com (8.13.1/8.13.1) with ESMTP id nB27sKG7006571 for ; Wed, 2 Dec 2009 07:54:20 GMT Received: from d12av04.megacenter.de.ibm.com (d12av04.megacenter.de.ibm.com [9.149.165.229]) by d12nrmr1607.megacenter.de.ibm.com (8.13.8/8.13.8/NCO v10.0) with ESMTP id nB27sKUt1249348 for ; Wed, 2 Dec 2009 08:54:20 +0100 Received: from d12av04.megacenter.de.ibm.com (loopback [127.0.0.1]) by d12av04.megacenter.de.ibm.com (8.12.11.20060308/8.13.3) with ESMTP id nB27sKDT005579 for ; Wed, 2 Dec 2009 08:54:20 +0100 Message-ID: <4B161D54.6010600@de.ibm.com> Date: Wed, 02 Dec 2009 08:55:00 +0100 From: Carsten Otte MIME-Version: 1.0 Subject: Re: [Qemu-devel] [PATCH 01/11] S/390 CPU fake emulation References: <1259241800-2810-1-git-send-email-agraf@suse.de> <1259241800-2810-2-git-send-email-agraf@suse.de> <20091130181838.GA17595@volta.aurel32.net> <47F0CA71-B478-4E4A-8468-B71137363E78@suse.de> <4B14E5DD.9080504@de.ibm.com> In-Reply-To: Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Blue Swirl Cc: Carsten Otte , Alexander Graf , Aurelien Jarno , qemu-devel@nongnu.org Blue Swirl wrote: > The translation block (TB) refers to a block of host instructions, > translated from some block of target instructions under some > assumptions. The assumptions used when translating (for example, user > vs supervisor mode in the CPU state) are recorded to TB flags. If the > CPU state changes, the old TBs with different flags will not be used > and new TBs will be generated. Thanks for the explanation, Alex did explain it too on irc. > Actually Sparc64 address spaces and ASIs are very similar. There are > nucleus, primary and secondary address spaces (not fully implemented > yet in QEMU). Instructions can encode the ASI or %asi register can be > used. Some ASIs are restricted for supervisor or hypervisor modes. > Sparc32 ASIs are simpler (physical address space extension to 36 bits, > basically) and for supervisor only. Oh, I though we were the only odd bird on this one. > For S/390, I think the TB flags do not need to contain the address > space control registers if the generated instructions fetch the state > from CPU state and do not rely on translation time information. If the > address spaces do not change very often, it may alternatively be > possible to rely on the CPU state during translation, but then it must > be ensured that all generated TBs are always flushed when the > registers change. Yes, that would work as far as I can tell. The registers change whenever $guest decides to schedule a different task, but not on every syscall. cheers, Carsten