From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mailman by lists.gnu.org with tmda-scanned (Exim 4.43) id 1NK79l-000723-6u for qemu-devel@nongnu.org; Mon, 14 Dec 2009 04:23:53 -0500 Received: from exim by lists.gnu.org with spam-scanned (Exim 4.43) id 1NK79g-000706-Ib for qemu-devel@nongnu.org; Mon, 14 Dec 2009 04:23:52 -0500 Received: from [199.232.76.173] (port=35457 helo=monty-python.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1NK79g-0006zv-7i for qemu-devel@nongnu.org; Mon, 14 Dec 2009 04:23:48 -0500 Received: from dns.vtab.com ([62.20.90.195]:48501 helo=oden.vtab.com) by monty-python.gnu.org with esmtps (TLS-1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.60) (envelope-from ) id 1NK79f-000655-RY for qemu-devel@nongnu.org; Mon, 14 Dec 2009 04:23:48 -0500 Message-ID: <4B26041B.20902@virtutech.com> Date: Mon, 14 Dec 2009 10:23:39 +0100 From: Magnus Christensson MIME-Version: 1.0 References: <20091213151249.GA22854@morn.localdomain> In-Reply-To: <20091213151249.GA22854@morn.localdomain> Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Subject: [Qemu-devel] Re: Seabios: PCI interrupt routing question List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Kevin O'Connor Cc: qemu-devel@nongnu.org, Gleb Natapov On 12/13/2009 04:12 PM, Kevin O'Connor wrote: > ----- Forwarded message from Gleb Natapov ----- > > From: Gleb Natapov > To: Kevin O'Connor > Date: Sun, 13 Dec 2009 17:07:48 +0200 > Subject: Re: [mch@virtutech.com: [coreboot] Seabios: PCI interrupt routing > question] > > On Thu, Dec 10, 2009 at 08:55:11AM -0500, Kevin O'Connor wrote: > >> FYI. >> >> ----- Forwarded message from Magnus Christensson ----- >> >> From: Magnus Christensson >> To: coreboot@coreboot.org >> Date: Fri, 27 Nov 2009 09:13:02 +0100 >> Subject: [coreboot] Seabios: PCI interrupt routing question >> >> Hi, >> >> I have a question about the PCI INTx pin interrupt routing in Seabios. >> >> Specifically, what does the pci_slot_get_pirq function do? It looks like >> it assigns different interrupt numbers to devices depending on their >> device number. >> >> > This function implement the same logic as pci_swizzle_interrupt_pin() in > Linux kernel. This logic defines how PCI bridge connects INTx of each > devices behind it to system board interrupt line and it is part of PCI > spec (page 30 of PCI3.0 spec). Note that the function return pin, not > interrupt line. To get interrupt line we look into pci_irqs[] array. > The swizzling of INTx-pins happens in PCI-to-PCI bridges. But it looks like the pci_slot_get_pirq function is applied to all devices, including those on the top-level bus that are not behind any PCI-to-PCI bridge. Further, the function only looks at device (slot) and doesn't care where the device is in the PCI hierarchy. > >> But the interrupt routing in the southbridge maps a given INTx to the same >> interrupt number regardless of the device number (that mapping is >> initialized by the code with the "activate irq remapping in PIIX" comment). >> >> To me, this looks like the INTERRUPT_LINE would be set to a value that >> does not match the actual interrupt routing (if (dev& 3) != 0). >> >> > The code is correct if QEMU does interrupt swizzling on PIIX3 chipset > level. The code in incorrect if QEMU doesn't. Swizzling like this is > done by PCI-to-PCI bridges according to PCI spec, root bridge doesn't do > it AFAIK, so code looks suspicious, but not because of the reason stated > above. > Yes, if the QEMU emulation of PIIX3 does swizzling on bus #0 (which I don't think happens in hardware), then the code would be correct (for running on QEMU). M.