From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mailman by lists.gnu.org with tmda-scanned (Exim 4.43) id 1NN7IW-0004r2-Pi for qemu-devel@nongnu.org; Tue, 22 Dec 2009 11:09:20 -0500 Received: from exim by lists.gnu.org with spam-scanned (Exim 4.43) id 1NN7IV-0004q2-59 for qemu-devel@nongnu.org; Tue, 22 Dec 2009 11:09:20 -0500 Received: from [199.232.76.173] (port=48497 helo=monty-python.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1NN7IV-0004pz-0b for qemu-devel@nongnu.org; Tue, 22 Dec 2009 11:09:19 -0500 Received: from are.twiddle.net ([75.149.56.221]:34222) by monty-python.gnu.org with esmtp (Exim 4.60) (envelope-from ) id 1NN7IT-0000Sr-FA for qemu-devel@nongnu.org; Tue, 22 Dec 2009 11:09:18 -0500 Message-ID: <4B30EF22.3000409@twiddle.net> Date: Tue, 22 Dec 2009 08:09:06 -0800 From: Richard Henderson MIME-Version: 1.0 Subject: Re: [Qemu-devel] [PATCH 1/5] tcg: Generic support for conditional set References: <08eb5a18dde9c9a676073d179003398473ca311c.1261248772.git.rth@twiddle.net> <761ea48b0912220327g8184dddu20323f5c32cd390a@mail.gmail.com> In-Reply-To: <761ea48b0912220327g8184dddu20323f5c32cd390a@mail.gmail.com> Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Laurent Desnogues Cc: qemu-devel@nongnu.org, aurelien@aurel32.net On 12/22/2009 03:27 AM, Laurent Desnogues wrote: >> +#if TCG_TARGET_REG_BITS == 64 >> + tcg_gen_op4i_i64(INDEX_op_setcond_i64, ret, arg1, arg2, cond); >> +#else >> + tcg_gen_op6i_i32(INDEX_op_setcond2_i32, TCGV_LOW(ret), >> + TCGV_LOW(arg1), TCGV_HIGH(arg1), >> + TCGV_LOW(arg2), TCGV_HIGH(arg2), cond); >> + tcg_gen_movi_i32(TCGV_HIGH(ret), 0); >> +#endif >> +} > > I wonder if it wouldn't be better to let the back-ends emit the > clearing of TCGV_HIGH(ret). This would reduce the number > of emitted TCG ops. Any thoughts? (1) That would require 6 registers on i386 simultaneously. (2) You lose the constant propagation that TCG would perform. r~