From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mailman by lists.gnu.org with tmda-scanned (Exim 4.43) id 1NVSCx-0002R9-ND for qemu-devel@nongnu.org; Thu, 14 Jan 2010 11:06:03 -0500 Received: from exim by lists.gnu.org with spam-scanned (Exim 4.43) id 1NVSCw-0002PE-GJ for qemu-devel@nongnu.org; Thu, 14 Jan 2010 11:06:03 -0500 Received: from [199.232.76.173] (port=51487 helo=monty-python.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1NVSCw-0002Ow-8V for qemu-devel@nongnu.org; Thu, 14 Jan 2010 11:06:02 -0500 Received: from are.twiddle.net ([75.149.56.221]:52769) by monty-python.gnu.org with esmtp (Exim 4.60) (envelope-from ) id 1NVSCv-0003cC-OV for qemu-devel@nongnu.org; Thu, 14 Jan 2010 11:06:01 -0500 Message-ID: <4B4F40E6.9040509@twiddle.net> Date: Thu, 14 Jan 2010 08:05:58 -0800 From: Richard Henderson MIME-Version: 1.0 Subject: Re: [Qemu-devel] [PATCH 1/2] tcg-x86_64: Special-case all 32-bit AND operands. References: <20100106010536.9092BCBA@are.twiddle.net> <20100114155727.GE16630@volta.aurel32.net> In-Reply-To: <20100114155727.GE16630@volta.aurel32.net> Content-Type: text/plain; charset=ISO-8859-15; format=flowed Content-Transfer-Encoding: 7bit List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Aurelien Jarno Cc: laurent.desnogues@gmail.com, qemu-devel@nongnu.org On 01/14/2010 07:57 AM, Aurelien Jarno wrote: > On Tue, Jan 05, 2010 at 04:03:00PM -0800, Richard Henderson wrote: >> This avoids an unnecessary REX.W prefix when dealing with AND >> operands that fit into a 32-bit quantity. The most common change >> actually seen is movz[wb]q -> movz[wb]l. >> >> Similarly, avoid REXW in ext{8,16}u_i64 tcg opcodes. >> >> Signed-off-by: Richard Henderson >> --- >> tcg/x86_64/tcg-target.c | 26 ++++++++------------------ >> 1 files changed, 8 insertions(+), 18 deletions(-) >> >> diff --git a/tcg/x86_64/tcg-target.c b/tcg/x86_64/tcg-target.c >> index 2339091..f584c94 100644 >> --- a/tcg/x86_64/tcg-target.c >> +++ b/tcg/x86_64/tcg-target.c >> @@ -426,24 +426,18 @@ static inline void tgen_arithi64(TCGContext *s, int c, int r0, int64_t val) >> } else if ((c == ARITH_ADD&& val == -1) || (c == ARITH_SUB&& val == 1)) { >> /* dec */ >> tcg_out_modrm(s, 0xff | P_REXW, 1, r0); >> - } else if (val == (int8_t)val) { >> - tcg_out_modrm(s, 0x83 | P_REXW, c, r0); >> - tcg_out8(s, val); >> - } else if (c == ARITH_AND&& val == 0xffu) { >> - /* movzbl */ >> - tcg_out_modrm(s, 0xb6 | P_EXT | P_REXW, r0, r0); >> - } else if (c == ARITH_AND&& val == 0xffffu) { >> - /* movzwl */ >> - tcg_out_modrm(s, 0xb7 | P_EXT | P_REXW, r0, r0); >> } else if (c == ARITH_AND&& val == 0xffffffffu) { >> /* 32-bit mov zero extends */ >> tcg_out_modrm(s, 0x8b, r0, r0); >> + } else if (c == ARITH_AND&& (uint64_t)val<= 0xffffffffu) { >> + /* AND with no high bits set can use a 32-bit operation. */ >> + tgen_arithi32(s, c, r0, val); > > Do we really want to call tgen_arithi32() here, that will redo part of > the above tests again? It might be better to simply remove the REX.W > prefix above instead. Pardon? Do you mean the inc/dec tests? Otherwise I don't see what "above tests again" you're talking about. I am looking to handle more than 0xff, 0xffff with the new test in gen_arithi64 -- 0x1234 is an appropriate mask to shorten to 32-bit AND as well. I have no idea if that answers your question. r~