From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mailman by lists.gnu.org with tmda-scanned (Exim 4.43) id 1NfJtA-0003hW-Bi for qemu-devel@nongnu.org; Wed, 10 Feb 2010 16:14:24 -0500 Received: from [199.232.76.173] (port=37199 helo=monty-python.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1NfJt9-0003hJ-0e for qemu-devel@nongnu.org; Wed, 10 Feb 2010 16:14:23 -0500 Received: from Debian-exim by monty-python.gnu.org with spam-scanned (Exim 4.60) (envelope-from ) id 1NfJt7-0008I1-Ib for qemu-devel@nongnu.org; Wed, 10 Feb 2010 16:14:22 -0500 Received: from mail-iw0-f194.google.com ([209.85.223.194]:41236) by monty-python.gnu.org with esmtp (Exim 4.60) (envelope-from ) id 1NfJt6-0008EO-0m for qemu-devel@nongnu.org; Wed, 10 Feb 2010 16:14:21 -0500 Received: by iwn32 with SMTP id 32so852059iwn.14 for ; Wed, 10 Feb 2010 13:13:31 -0800 (PST) Message-ID: <4B732179.8020901@codemonkey.ws> Date: Wed, 10 Feb 2010 15:13:29 -0600 From: Anthony Liguori MIME-Version: 1.0 Subject: Re: [Qemu-devel] [PATCH 0/15][RFC] New PCI interfaces References: <1265752899-26980-1-git-send-email-aliguori@us.ibm.com> <4B73090E.1020408@codemonkey.ws> <4B7319F6.5050506@twiddle.net> In-Reply-To: <4B7319F6.5050506@twiddle.net> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Richard Henderson Cc: Blue Swirl , Michael Tsirkin , qemu-devel@nongnu.org, Alex Graf On 02/10/2010 02:41 PM, Richard Henderson wrote: > On 02/10/2010 11:29 AM, Anthony Liguori wrote: >> void *pci_memory_map(PCIDevice *dev, pcibus_t addr, pcibus_t *plen, int >> is_write); >> >> void pci_memory_unmap(PCIDevice *dev, void *buf, pcibus_t *plen, int >> is_write, pcibus_t access_len); > > Are these functions intended to be controllable by the root bus > object? It would be awfully nice if we would design in a hook that > allowed iommu mapping to be done properly. Yes, that's the point. For something like virtio, you would have a call chain like: virtio_memory_map -> pci_memory_map -> sysbus_memory_map[1] -> cpu_memory_map. Each layer has the ability to do things like implement iommu mapping. [1] I think it might make sense to have a sysbus layer but I'm not 100% sure yet. Regards, Anthony Liguori > > r~