From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mailman by lists.gnu.org with tmda-scanned (Exim 4.43) id 1NiGfC-0004l2-9p for qemu-devel@nongnu.org; Thu, 18 Feb 2010 19:24:10 -0500 Received: from [199.232.76.173] (port=53340 helo=monty-python.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1NiGfB-0004ki-V7 for qemu-devel@nongnu.org; Thu, 18 Feb 2010 19:24:09 -0500 Received: from Debian-exim by monty-python.gnu.org with spam-scanned (Exim 4.60) (envelope-from ) id 1NiGf9-0005vb-NM for qemu-devel@nongnu.org; Thu, 18 Feb 2010 19:24:09 -0500 Received: from [75.150.230.173] (port=28917 helo=us2.astc-design.com) by monty-python.gnu.org with smtp (Exim 4.60) (envelope-from ) id 1NiGey-0005uV-Ru for qemu-devel@nongnu.org; Thu, 18 Feb 2010 19:24:07 -0500 Received: from f14.astc-design.net (unknown [172.18.136.254]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (Client CN "George Karavaev", Issuer "ASTC Pty Ltd CA" (verified OK)) by us2.astc-design.com (Postfix) with ESMTP id 46066CC08C for ; Thu, 18 Feb 2010 17:56:03 -0600 (CST) Message-ID: <4B7DD393.7070809@astc-design.com> Date: Thu, 18 Feb 2010 17:56:03 -0600 From: George Karavaev MIME-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Subject: [Qemu-devel] [PATCH] Added Cortex_a8_v3 version, and added a shift instruction for NEON. List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org --- target-arm/cpu.h | 1 + target-arm/helper.c | 3 +++ target-arm/translate.c | 17 +++++++++++++++-- 3 files changed, 19 insertions(+), 2 deletions(-) diff --git a/target-arm/cpu.h b/target-arm/cpu.h index 4a1c53f..8751402 100644 --- a/target-arm/cpu.h +++ b/target-arm/cpu.h @@ -392,6 +392,7 @@ void cpu_arm_set_cp_io(CPUARMState *env, int cpnum, #define ARM_CPUID_ARM1136_R2 0x4107b362 #define ARM_CPUID_ARM11MPCORE 0x410fb022 #define ARM_CPUID_CORTEXA8 0x410fc080 +#define ARM_CPUID_CORTEXA8_V3 0x410fc083 #define ARM_CPUID_CORTEXA9 0x410fc090 #define ARM_CPUID_CORTEXM3 0x410fc231 #define ARM_CPUID_ANY 0xffffffff diff --git a/target-arm/helper.c b/target-arm/helper.c index 27001e8..65e88b0 100644 --- a/target-arm/helper.c +++ b/target-arm/helper.c @@ -87,6 +87,7 @@ static void cpu_reset_model_id(CPUARMState *env, uint32_t id) env->cp15.c0_cachetype = 0x1dd20d2; break; case ARM_CPUID_CORTEXA8: + case ARM_CPUID_CORTEXA8_V3: set_feature(env, ARM_FEATURE_V6); set_feature(env, ARM_FEATURE_V6K); set_feature(env, ARM_FEATURE_V7); @@ -314,6 +315,7 @@ static const struct arm_cpu_t arm_cpu_names[] = { { ARM_CPUID_ARM11MPCORE, "arm11mpcore"}, { ARM_CPUID_CORTEXM3, "cortex-m3"}, { ARM_CPUID_CORTEXA8, "cortex-a8"}, + { ARM_CPUID_CORTEXA8_V3, "cortex-a8-v3"}, { ARM_CPUID_CORTEXA9, "cortex-a9"}, { ARM_CPUID_TI925T, "ti925t" }, { ARM_CPUID_PXA250, "pxa250" }, @@ -1634,6 +1636,7 @@ uint32_t HELPER(get_cp15)(CPUState *env, uint32_t insn) case ARM_CPUID_ARM11MPCORE: return 1; case ARM_CPUID_CORTEXA8: + case ARM_CPUID_CORTEXA8_V3: return 2; case ARM_CPUID_CORTEXA9: return 0; diff --git a/target-arm/translate.c b/target-arm/translate.c index 786c329..c389ee6 100644 --- a/target-arm/translate.c +++ b/target-arm/translate.c @@ -4658,9 +4658,22 @@ static int disas_neon_data_insn(CPUState * env, DisasContext *s, uint32_t insn) /* Accumulate. */ neon_load_reg64(cpu_V0, rd + pass); tcg_gen_add_i64(cpu_V0, cpu_V0, cpu_V1); - } else if (op == 4 || (op == 5 && u)) { + } else if (op == 4) { + /* Insert - VSRI */ /* Insert */ - cpu_abort(env, "VS[LR]I.64 not implemented"); + cpu_abort(env, "VSRI.64 not implemented"); + } else if (op == 5 && u) { + /* Insert - VSLI */ + tmp64 = tcg_temp_new_i64(); + tcg_gen_movi_i64(tmp64, 0); + tcg_gen_not_i64(tmp64, tmp64); + gen_helper_neon_shl_u64(tmp64, tmp64, cpu_V1); + tcg_gen_and_i64(cpu_V0, cpu_V0, tmp64); /* XXX */ + tcg_gen_not_i64(tmp64, tmp64); + neon_load_reg64(cpu_V1, rd + pass); + tcg_gen_and_i64(cpu_V1, cpu_V1, tmp64); + tcg_temp_free_i64(tmp64); + tcg_gen_or_i64(cpu_V0, cpu_V0, cpu_V1); } neon_store_reg64(cpu_V0, rd + pass); } else { /* size < 3 */ -- 1.6.4.4