* [Qemu-devel] [PATCH] Added Cortex_a8_v3 version, and added a shift instruction for NEON.
@ 2010-02-18 23:56 George Karavaev
2010-02-19 15:52 ` Richard Henderson
0 siblings, 1 reply; 3+ messages in thread
From: George Karavaev @ 2010-02-18 23:56 UTC (permalink / raw)
To: qemu-devel
---
target-arm/cpu.h | 1 +
target-arm/helper.c | 3 +++
target-arm/translate.c | 17 +++++++++++++++--
3 files changed, 19 insertions(+), 2 deletions(-)
diff --git a/target-arm/cpu.h b/target-arm/cpu.h
index 4a1c53f..8751402 100644
--- a/target-arm/cpu.h
+++ b/target-arm/cpu.h
@@ -392,6 +392,7 @@ void cpu_arm_set_cp_io(CPUARMState *env, int cpnum,
#define ARM_CPUID_ARM1136_R2 0x4107b362
#define ARM_CPUID_ARM11MPCORE 0x410fb022
#define ARM_CPUID_CORTEXA8 0x410fc080
+#define ARM_CPUID_CORTEXA8_V3 0x410fc083
#define ARM_CPUID_CORTEXA9 0x410fc090
#define ARM_CPUID_CORTEXM3 0x410fc231
#define ARM_CPUID_ANY 0xffffffff
diff --git a/target-arm/helper.c b/target-arm/helper.c
index 27001e8..65e88b0 100644
--- a/target-arm/helper.c
+++ b/target-arm/helper.c
@@ -87,6 +87,7 @@ static void cpu_reset_model_id(CPUARMState *env,
uint32_t id)
env->cp15.c0_cachetype = 0x1dd20d2;
break;
case ARM_CPUID_CORTEXA8:
+ case ARM_CPUID_CORTEXA8_V3:
set_feature(env, ARM_FEATURE_V6);
set_feature(env, ARM_FEATURE_V6K);
set_feature(env, ARM_FEATURE_V7);
@@ -314,6 +315,7 @@ static const struct arm_cpu_t arm_cpu_names[] = {
{ ARM_CPUID_ARM11MPCORE, "arm11mpcore"},
{ ARM_CPUID_CORTEXM3, "cortex-m3"},
{ ARM_CPUID_CORTEXA8, "cortex-a8"},
+ { ARM_CPUID_CORTEXA8_V3, "cortex-a8-v3"},
{ ARM_CPUID_CORTEXA9, "cortex-a9"},
{ ARM_CPUID_TI925T, "ti925t" },
{ ARM_CPUID_PXA250, "pxa250" },
@@ -1634,6 +1636,7 @@ uint32_t HELPER(get_cp15)(CPUState *env, uint32_t
insn)
case ARM_CPUID_ARM11MPCORE:
return 1;
case ARM_CPUID_CORTEXA8:
+ case ARM_CPUID_CORTEXA8_V3:
return 2;
case ARM_CPUID_CORTEXA9:
return 0;
diff --git a/target-arm/translate.c b/target-arm/translate.c
index 786c329..c389ee6 100644
--- a/target-arm/translate.c
+++ b/target-arm/translate.c
@@ -4658,9 +4658,22 @@ static int disas_neon_data_insn(CPUState * env,
DisasContext *s, uint32_t insn)
/* Accumulate. */
neon_load_reg64(cpu_V0, rd + pass);
tcg_gen_add_i64(cpu_V0, cpu_V0, cpu_V1);
- } else if (op == 4 || (op == 5 && u)) {
+ } else if (op == 4) {
+ /* Insert - VSRI */
/* Insert */
- cpu_abort(env, "VS[LR]I.64 not implemented");
+ cpu_abort(env, "VSRI.64 not implemented");
+ } else if (op == 5 && u) {
+ /* Insert - VSLI */
+ tmp64 = tcg_temp_new_i64();
+ tcg_gen_movi_i64(tmp64, 0);
+ tcg_gen_not_i64(tmp64, tmp64);
+ gen_helper_neon_shl_u64(tmp64, tmp64, cpu_V1);
+ tcg_gen_and_i64(cpu_V0, cpu_V0, tmp64); /*
XXX */
+ tcg_gen_not_i64(tmp64, tmp64);
+ neon_load_reg64(cpu_V1, rd + pass);
+ tcg_gen_and_i64(cpu_V1, cpu_V1, tmp64);
+ tcg_temp_free_i64(tmp64);
+ tcg_gen_or_i64(cpu_V0, cpu_V0, cpu_V1);
}
neon_store_reg64(cpu_V0, rd + pass);
} else { /* size < 3 */
--
1.6.4.4
^ permalink raw reply related [flat|nested] 3+ messages in thread
* Re: [Qemu-devel] [PATCH] Added Cortex_a8_v3 version, and added a shift instruction for NEON.
2010-02-18 23:56 [Qemu-devel] [PATCH] Added Cortex_a8_v3 version, and added a shift instruction for NEON George Karavaev
@ 2010-02-19 15:52 ` Richard Henderson
2010-03-03 0:33 ` [Qemu-devel] " George Karavaev
0 siblings, 1 reply; 3+ messages in thread
From: Richard Henderson @ 2010-02-19 15:52 UTC (permalink / raw)
To: George Karavaev; +Cc: qemu-devel
On 02/18/2010 03:56 PM, George Karavaev wrote:
> + tmp64 = tcg_temp_new_i64();
> + tcg_gen_movi_i64(tmp64, 0);
> + tcg_gen_not_i64(tmp64, tmp64);
movi -1?
> + gen_helper_neon_shl_u64(tmp64, tmp64, cpu_V1);
> + tcg_gen_and_i64(cpu_V0, cpu_V0, tmp64); /*
> XXX */
Why the XXX?
> + tcg_gen_not_i64(tmp64, tmp64);
> + tcg_gen_and_i64(cpu_V1, cpu_V1, tmp64);
tcg_gen_andc_i64.
r~
^ permalink raw reply [flat|nested] 3+ messages in thread
* [Qemu-devel] Re: [PATCH] Added Cortex_a8_v3 version, and added a shift instruction for NEON.
2010-02-19 15:52 ` Richard Henderson
@ 2010-03-03 0:33 ` George Karavaev
0 siblings, 0 replies; 3+ messages in thread
From: George Karavaev @ 2010-03-03 0:33 UTC (permalink / raw)
To: qemu-devel
Here's the patch after suggested changes.
---
target-arm/cpu.h | 1 +
target-arm/helper.c | 3 +++
target-arm/translate.c | 16 +++++++++++++---
3 files changed, 17 insertions(+), 3 deletions(-)
diff --git a/target-arm/cpu.h b/target-arm/cpu.h
index 4a1c53f..8751402 100644
--- a/target-arm/cpu.h
+++ b/target-arm/cpu.h
@@ -392,6 +392,7 @@ void cpu_arm_set_cp_io(CPUARMState *env, int cpnum,
#define ARM_CPUID_ARM1136_R2 0x4107b362
#define ARM_CPUID_ARM11MPCORE 0x410fb022
#define ARM_CPUID_CORTEXA8 0x410fc080
+#define ARM_CPUID_CORTEXA8_V3 0x410fc083
#define ARM_CPUID_CORTEXA9 0x410fc090
#define ARM_CPUID_CORTEXM3 0x410fc231
#define ARM_CPUID_ANY 0xffffffff
diff --git a/target-arm/helper.c b/target-arm/helper.c
index 6f40084..ed0b476 100644
--- a/target-arm/helper.c
+++ b/target-arm/helper.c
@@ -87,6 +87,7 @@ static void cpu_reset_model_id(CPUARMState *env,
uint32_t id)
env->cp15.c0_cachetype = 0x1dd20d2;
break;
case ARM_CPUID_CORTEXA8:
+ case ARM_CPUID_CORTEXA8_V3:
set_feature(env, ARM_FEATURE_V6);
set_feature(env, ARM_FEATURE_V6K);
set_feature(env, ARM_FEATURE_V7);
@@ -314,6 +315,7 @@ static const struct arm_cpu_t arm_cpu_names[] = {
{ ARM_CPUID_ARM11MPCORE, "arm11mpcore"},
{ ARM_CPUID_CORTEXM3, "cortex-m3"},
{ ARM_CPUID_CORTEXA8, "cortex-a8"},
+ { ARM_CPUID_CORTEXA8_V3, "cortex-a8-v3"},
{ ARM_CPUID_CORTEXA9, "cortex-a9"},
{ ARM_CPUID_TI925T, "ti925t" },
{ ARM_CPUID_PXA250, "pxa250" },
@@ -1633,6 +1635,7 @@ uint32_t HELPER(get_cp15)(CPUState *env, uint32_t
insn)
case ARM_CPUID_ARM11MPCORE:
return 1;
case ARM_CPUID_CORTEXA8:
+ case ARM_CPUID_CORTEXA8_V3:
return 2;
case ARM_CPUID_CORTEXA9:
return 0;
diff --git a/target-arm/translate.c b/target-arm/translate.c
index 9607aae..5474408 100644
--- a/target-arm/translate.c
+++ b/target-arm/translate.c
@@ -4656,9 +4656,19 @@ static int disas_neon_data_insn(CPUState * env,
DisasContext *s, uint32_t insn)
/* Accumulate. */
neon_load_reg64(cpu_V0, rd + pass);
tcg_gen_add_i64(cpu_V0, cpu_V0, cpu_V1);
- } else if (op == 4 || (op == 5 && u)) {
- /* Insert */
- cpu_abort(env, "VS[LR]I.64 not implemented");
+ } else if (op == 4) {
+ /* Insert - VSRI */
+ cpu_abort(env, "VSRI.64 not implemented");
+ } else if (op == 5 && u) {
+ /* VSLI */
+ tmp64 = tcg_temp_new_i64();
+ tcg_gen_movi_i64(tmp64, -1);
+ gen_helper_neon_shl_u64(tmp64, tmp64, cpu_V1);
+ tcg_gen_and_i64(cpu_V0, cpu_V0, tmp64);
+ neon_load_reg64(cpu_V1, rd + pass);
+ tcg_gen_andc_i64(cpu_V1, cpu_V1, tmp64);
+ tcg_temp_free_i64(tmp64);
+ tcg_gen_or_i64(cpu_V0, cpu_V0, cpu_V1);
}
neon_store_reg64(cpu_V0, rd + pass);
} else { /* size < 3 */
--
1.6.4.4
^ permalink raw reply related [flat|nested] 3+ messages in thread
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2010-02-18 23:56 [Qemu-devel] [PATCH] Added Cortex_a8_v3 version, and added a shift instruction for NEON George Karavaev
2010-02-19 15:52 ` Richard Henderson
2010-03-03 0:33 ` [Qemu-devel] " George Karavaev
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