From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mailman by lists.gnu.org with tmda-scanned (Exim 4.43) id 1NjbcR-0006YK-5S for qemu-devel@nongnu.org; Mon, 22 Feb 2010 11:58:51 -0500 Received: from [199.232.76.173] (port=50843 helo=monty-python.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1NjbcQ-0006XH-GN for qemu-devel@nongnu.org; Mon, 22 Feb 2010 11:58:50 -0500 Received: from Debian-exim by monty-python.gnu.org with spam-scanned (Exim 4.60) (envelope-from ) id 1NjbcN-0004QU-BB for qemu-devel@nongnu.org; Mon, 22 Feb 2010 11:58:50 -0500 Received: from moutng.kundenserver.de ([212.227.126.171]:62790) by monty-python.gnu.org with esmtp (Exim 4.60) (envelope-from ) id 1NjbcM-0004QQ-Rl for qemu-devel@nongnu.org; Mon, 22 Feb 2010 11:58:47 -0500 Message-ID: <4B82B7C4.3000701@mail.berlios.de> Date: Mon, 22 Feb 2010 17:58:44 +0100 From: Stefan Weil MIME-Version: 1.0 Subject: Re: [Qemu-devel] [PATCH] tcg: fix build on 32-bit hppa, ppc and sparc hosts References: <4B82B244.6040402@mail.berlios.de> In-Reply-To: Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Jay Foad Cc: qemu-devel@nongnu.org, Alexander Graf Jay Foad schrieb: >>> --- a/tcg/ppc/tcg-target.c >>> +++ b/tcg/ppc/tcg-target.c >>> @@ -1693,7 +1693,6 @@ static const TCGTargetOpDef ppc_op_defs[] = { >>> { INDEX_op_qemu_ld16u, { "r", "L" } }, >>> { INDEX_op_qemu_ld16s, { "r", "L" } }, >>> { INDEX_op_qemu_ld32u, { "r", "L" } }, >>> - { INDEX_op_qemu_ld32s, { "r", "L" } }, >>> >>> >> No. As I wrote in the original thread, >> conditional compilation is needed here >> (or you will get new compile errors). >> > > In tcg/ppc/, TCG_TARGET_REG_BITS is always 32, isn't it? > > Thanks, > Jay. > Yes, you are right. Please excuse my wrong feedback. Stefan