From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mailman by lists.gnu.org with tmda-scanned (Exim 4.43) id 1Np7Ej-0007AJ-AR for qemu-devel@nongnu.org; Tue, 09 Mar 2010 16:45:09 -0500 Received: from [199.232.76.173] (port=45213 helo=monty-python.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1Np7Ei-00079v-Rn for qemu-devel@nongnu.org; Tue, 09 Mar 2010 16:45:08 -0500 Received: from Debian-exim by monty-python.gnu.org with spam-scanned (Exim 4.60) (envelope-from ) id 1Np7Eh-0001Gu-7U for qemu-devel@nongnu.org; Tue, 09 Mar 2010 16:45:08 -0500 Received: from mail-yw0-f190.google.com ([209.85.211.190]:62962) by monty-python.gnu.org with esmtp (Exim 4.60) (envelope-from ) id 1Np7Eh-0001Gk-0Q for qemu-devel@nongnu.org; Tue, 09 Mar 2010 16:45:07 -0500 Received: by ywh28 with SMTP id 28so6090666ywh.29 for ; Tue, 09 Mar 2010 13:45:05 -0800 (PST) Message-ID: <4B96C15A.2040600@codemonkey.ws> Date: Tue, 09 Mar 2010 15:44:58 -0600 From: Anthony Liguori MIME-Version: 1.0 Subject: Re: [Qemu-devel] [PATCH] Inter-VM shared memory PCI device References: <1267833161-25267-1-git-send-email-cam@cs.ualberta.ca> <201003072254.00040.paul@codesourcery.com> <4B94C8CD.2030808@redhat.com> <201003081303.45179.paul@codesourcery.com> <4B94F89B.3060504@redhat.com> In-Reply-To: <4B94F89B.3060504@redhat.com> Content-Type: text/plain; charset=ISO-8859-15; format=flowed Content-Transfer-Encoding: 7bit List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Avi Kivity Cc: Cam Macdonell , Paul Brook , kvm@vger.kernel.org, qemu-devel@nongnu.org On 03/08/2010 07:16 AM, Avi Kivity wrote: > On 03/08/2010 03:03 PM, Paul Brook wrote: >>> On 03/08/2010 12:53 AM, Paul Brook wrote: >>>>> Support an inter-vm shared memory device that maps a shared-memory >>>>> object as a PCI device in the guest. This patch also supports >>>>> interrupts between guest by communicating over a unix domain socket. >>>>> This patch applies to the qemu-kvm repository. >>>> No. All new devices should be fully qdev based. >>>> >>>> I suspect you've also ignored a load of coherency issues, >>>> especially when >>>> not using KVM. As soon as you have shared memory in more than one host >>>> thread/process you have to worry about memory barriers. >>> Shouldn't it be sufficient to require the guest to issue barriers (and >>> to ensure tcg honours the barriers, if someone wants this with tcg)?. >> In a cross environment that becomes extremely hairy. For example the >> x86 >> architecture effectively has an implicit write barrier before every >> store, and >> an implicit read barrier before every load. > > Ah yes. For cross tcg environments you can map the memory using mmio > callbacks instead of directly, and issue the appropriate barriers there. Not good enough unless you want to severely restrict the use of shared memory within the guest. For instance, it's going to be useful to assume that you atomic instructions remain atomic. Crossing architecture boundaries here makes these assumptions invalid. A barrier is not enough. Shared memory only makes sense when using KVM. In fact, we should actively disable the shared memory device when not using KVM. Regards, Anthony Liguori