From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mailman by lists.gnu.org with tmda-scanned (Exim 4.43) id 1Nurfv-000812-AG for qemu-devel@nongnu.org; Thu, 25 Mar 2010 14:20:59 -0400 Received: from [140.186.70.92] (port=42978 helo=eggs.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1Nurft-0007xg-QX for qemu-devel@nongnu.org; Thu, 25 Mar 2010 14:20:58 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.69) (envelope-from ) id 1Nureg-0000C1-Lw for qemu-devel@nongnu.org; Thu, 25 Mar 2010 14:19:44 -0400 Received: from are.twiddle.net ([75.149.56.221]:40961) by eggs.gnu.org with esmtp (Exim 4.69) (envelope-from ) id 1Nureg-0000Bv-B6 for qemu-devel@nongnu.org; Thu, 25 Mar 2010 14:19:42 -0400 Message-ID: <4BABA93C.9010305@twiddle.net> Date: Thu, 25 Mar 2010 11:19:40 -0700 From: Richard Henderson MIME-Version: 1.0 Subject: Re: [Qemu-devel] [PATCH 09/10] target-alpha: Implement load-locked/store-conditional properly. References: <20100325133920.GS16726@codesourcery.com> <4BAB853E.1070303@twiddle.net> In-Reply-To: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Blue Swirl Cc: aurelien@aurel32.net, qemu-devel@nongnu.org, Nathan Froyd On 03/25/2010 10:40 AM, Blue Swirl wrote: > Sparc V8 has two atomic instructions, ldstub and swap. I know -- but not the CAS operation being discussed here. As I think about this more and more, the Real Problem is not with the CAS, but with the memory ordering requirements of the guest vs the memory ordering of the host. It's easy to implement things on x86, because of the host's strict memory ordering. It would be much more difficult to properly emulate x86 on a relaxed memory ordering host. We'd need to insert barriers between pairs of qemu_{ld,st} operations. I may give this some proper thinking this weekend. r~