From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mailman by lists.gnu.org with tmda-scanned (Exim 4.43) id 1O4ZAt-0003oW-GX for qemu-devel@nongnu.org; Wed, 21 Apr 2010 08:37:03 -0400 Received: from [140.186.70.92] (port=55122 helo=eggs.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1O4ZAo-0003ls-Vc for qemu-devel@nongnu.org; Wed, 21 Apr 2010 08:37:02 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.69) (envelope-from ) id 1O4ZAi-0000V6-Ly for qemu-devel@nongnu.org; Wed, 21 Apr 2010 08:36:58 -0400 Received: from cantor.suse.de ([195.135.220.2]:58524 helo=mx1.suse.de) by eggs.gnu.org with esmtp (Exim 4.69) (envelope-from ) id 1O4ZAi-0000UH-Bn for qemu-devel@nongnu.org; Wed, 21 Apr 2010 08:36:52 -0400 Message-ID: <4BCEF15B.7020204@suse.de> Date: Wed, 21 Apr 2010 14:36:43 +0200 From: Alexander Graf MIME-Version: 1.0 Subject: Re: [Qemu-devel] [PATCH 2/2] target-ppc: fix interrupt vectors for MPC603 and e300 References: <1271841716-11582-1-git-send-email-thomas_ml@monjalon.net> <1271841716-11582-3-git-send-email-thomas_ml@monjalon.net> <9658034F-3621-4F6B-BBD7-CFDAF7E8BCDB@suse.de> <201004211407.50369.thomas_ml@monjalon.net> In-Reply-To: <201004211407.50369.thomas_ml@monjalon.net> Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Thomas Monjalon Cc: qemu-devel@nongnu.org, segher@kernel.crashing.org Thomas Monjalon wrote: > Alexander Graf wrote: > >>> --- a/target-ppc/translate_init.c >>> +++ b/target-ppc/translate_init.c >>> @@ -2853,7 +2853,16 @@ static void init_excp_603 (CPUPPCState *env) >>> env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400; >>> env->hreset_excp_prefix = 0x00000000UL; >>> /* Hardware reset vector */ >>> - env->hreset_vector = 0xFFFFFFFCUL; >>> + env->hreset_vector = 0x00000100UL; >>> >> Are you 100% sure this is correct? IIRC the reset vector is dictated by the >> CPU initialization sequence, so there's no hardwired value here really. >> > > It is explained in [e300CORERM] at chapters 5.2.3, 5.5.1.1 and 8.3.3. > Clearly, the vector offset is 0x100 and the exception prefix can be 0 or > 0xFFF00000, depending of the MSR[IP] bit. > > So, yes, I'm sure the value of hreset_vector must be 0x100. > But hreset_excp_prefix can change. It could be another patch. > Interesting. That's different from 970. > About the prefix initialization, the datasheet says it is "determined by > MSR[IP]". and is "determined by the state of the msrip signal". But I don't > understand what is the msrip signal and how MSR[IP] is changed (is it related > to msrip ?). Do you have an explanation for this part ? > I guess we should ask somebody more knowledgeable here. Segher? > >> Btw - what do you use to test your patches? >> > > I'm slowly writing support for the WindRiver board SBC8349E. > For the moment, I send patches for things I'm sure. > Nice. What kind of firmware does that use? Alex