From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from [140.186.70.92] (port=56335 helo=eggs.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1OCEQc-0003nP-OC for qemu-devel@nongnu.org; Wed, 12 May 2010 12:05:01 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.69) (envelope-from ) id 1OCEQZ-0006o0-4s for qemu-devel@nongnu.org; Wed, 12 May 2010 12:04:58 -0400 Received: from moutng.kundenserver.de ([212.227.126.187]:56028) by eggs.gnu.org with esmtp (Exim 4.69) (envelope-from ) id 1OCEQX-0006nN-Vk for qemu-devel@nongnu.org; Wed, 12 May 2010 12:04:54 -0400 Message-ID: <4BEAD194.1000702@mail.berlios.de> Date: Wed, 12 May 2010 18:04:36 +0200 From: Stefan Weil MIME-Version: 1.0 References: In-Reply-To: Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Subject: [Qemu-devel] Re: [PATCH 1/6] MIPS: Initial support of bonito north bridge used by fulong mini pc List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: chen huacai Cc: qemu-devel@nongnu.org, aurelien@aurel32.net Am 12.05.2010 10:50, schrieb chen huacai: > Signed-off-by: Huacai Chen > --- > Makefile.target | 1 + > default-configs/mips64el-softmmu.mak | 1 + > hw/bonito.c | 950 ++++++++++++++++++++++++++++++++++ > hw/mips.h | 3 + > 4 files changed, 955 insertions(+), 0 deletions(-) > create mode 100644 hw/bonito.c > > diff --git a/Makefile.target b/Makefile.target > index c092900..63d9f49 100644 > --- a/Makefile.target > +++ b/Makefile.target > @@ -220,6 +220,7 @@ obj-mips-y += dma.o vga.o i8259.o > obj-mips-y += g364fb.o jazz_led.o > obj-mips-y += gt64xxx.o pckbd.o mc146818rtc.o > obj-mips-y += piix4.o cirrus_vga.o > +obj-mips-$(CONFIG_FULONG) += bonito.o > > obj-microblaze-y = petalogix_s3adsp1800_mmu.o > > diff --git a/default-configs/mips64el-softmmu.mak > b/default-configs/mips64el-softmmu.mak > index b9b8c71..970568c 100644 > --- a/default-configs/mips64el-softmmu.mak > +++ b/default-configs/mips64el-softmmu.mak > @@ -26,3 +26,4 @@ CONFIG_DP8393X=y > CONFIG_DS1225Y=y > CONFIG_MIPSNET=y > CONFIG_PFLASH_CFI01=y > +CONFIG_FULONG=y > diff --git a/hw/bonito.c b/hw/bonito.c > new file mode 100644 > index 0000000..246c12a > --- /dev/null > +++ b/hw/bonito.c > @@ -0,0 +1,950 @@ > +/* > + * bonito north bridge support > + * > + * Copyright (c) 2008 yajin (yajin@vm-kernel.org) > + * Copyright (c) 2010 Huacai Chen (zltjiangshi@gmail.com) > + * > + * This code is licensed under the GNU GPL v2. > + */ > + > +/* > + * fulong 2e mini pc has a bonito north bridge. > + */ > + > +/* what is the meaning of devfn in qemu and IDSEL in bonito northbridge? > + * > + * devfn pci_slot<<3 + funno > + * one pci bus can have 32 devices and each device can have 8 functions. > + * > + * In bonito north bridge, pci slot = IDSEL bit - 12. > + * For example, PCI_IDSEL_VIA686B = 17, > + * pci slot = 17-12=5 > + * > + * so > + * VT686B_FUN0's devfn = (5<<3)+0 > + * VT686B_FUN1's devfn = (5<<3)+1 > + * > + * qemu also uses pci address for north bridge to access pci config register. > + * bus_no [23:16] > + * dev_no [15:11] > + * fun_no [10:8] > + * reg_no [7:2] > + * > + * so function bonito_sbridge_pciaddr for the translation from > + * north bridge address to pci address. > + */ > + > +#include > + > +#include "hw.h" > +#include "pci.h" > +#include "pc.h" > +#include "mips.h" > + > +typedef target_phys_addr_t pci_addr_t; > +#include "pci_host.h" > + > +//#define DEBUG_BONITO > + > +#ifdef DEBUG_BONITO > +#define DPRINTF(fmt, ...) fprintf(stderr, "%s: " fmt, __FUNCTION__, > ##__VA_ARGS__) > +#else > +#define DPRINTF(fmt, ...) > +#endif > + > +/* from linux soure code. include/asm-mips/mips-boards/bonito64.h*/ > +#define BONITO_BOOT_BASE 0x1fc00000 > +#define BONITO_BOOT_SIZE 0x00100000 > +#define BONITO_BOOT_TOP (BONITO_BOOT_BASE+BONITO_BOOT_SIZE-1) > +#define BONITO_FLASH_BASE 0x1c000000 > +#define BONITO_FLASH_SIZE 0x03000000 > +#define BONITO_FLASH_TOP (BONITO_FLASH_BASE+BONITO_FLASH_SIZE-1) > +#define BONITO_SOCKET_BASE 0x1f800000 > +#define BONITO_SOCKET_SIZE 0x00400000 > +#define BONITO_SOCKET_TOP (BONITO_SOCKET_BASE+BONITO_SOCKET_SIZE-1) > +#define BONITO_REG_BASE 0x1fe00000 > +#define BONITO_REG_SIZE 0x00040000 > +#define BONITO_REG_TOP (BONITO_REG_BASE+BONITO_REG_SIZE-1) > +#define BONITO_DEV_BASE 0x1ff00000 > +#define BONITO_DEV_SIZE 0x00100000 > +#define BONITO_DEV_TOP (BONITO_DEV_BASE+BONITO_DEV_SIZE-1) > +#define BONITO_PCILO_BASE 0x10000000 > +#define BONITO_PCILO_BASE_VA 0xb0000000 > +#define BONITO_PCILO_SIZE 0x0c000000 > +#define BONITO_PCILO_TOP (BONITO_PCILO_BASE+BONITO_PCILO_SIZE-1) > +#define BONITO_PCILO0_BASE 0x10000000 > +#define BONITO_PCILO1_BASE 0x14000000 > +#define BONITO_PCILO2_BASE 0x18000000 > +#define BONITO_PCIHI_BASE 0x20000000 > +#define BONITO_PCIHI_SIZE 0x20000000 > +#define BONITO_PCIHI_TOP (BONITO_PCIHI_BASE+BONITO_PCIHI_SIZE-1) > +#define BONITO_PCIIO_BASE 0x1fd00000 > +#define BONITO_PCIIO_BASE_VA 0xbfd00000 > +#define BONITO_PCIIO_SIZE 0x00010000 > +#define BONITO_PCIIO_TOP (BONITO_PCIIO_BASE+BONITO_PCIIO_SIZE-1) > +#define BONITO_PCICFG_BASE 0x1fe80000 > +#define BONITO_PCICFG_SIZE 0x00080000 > +#define BONITO_PCICFG_TOP (BONITO_PCICFG_BASE+BONITO_PCICFG_SIZE-1) > + > + > +#define BONITO_PCICONFIGBASE 0x00 > +#define BONITO_REGBASE 0x100 > + > +#define BONITO_PCICONFIG_BASE (BONITO_PCICONFIGBASE+BONITO_REG_BASE) > +#define BONITO_PCICONFIG_SIZE (0x100) > + > +#define BONITO_INTERNAL_REG_BASE (BONITO_REGBASE+BONITO_REG_BASE) > +#define BONITO_INTERNAL_REG_SIZE (0x70) > + > +#define BONITO_SPCICONFIG_BASE (BONITO_PCICFG_BASE) > +#define BONITO_SPCICONFIG_SIZE (BONITO_PCICFG_SIZE) > + > + > + > +/* 1. Bonito h/w Configuration */ > +/* Power on register */ > + > +#define BONITO_BONPONCFG (0x00>> 2) /* 0x100 */ > +#define BONITO_BONGENCFG_OFFSET 0x4 > +#define BONITO_BONGENCFG (BONITO_BONGENCFG_OFFSET>>2) /*0x104 */ > + > +/* 2. IO& IDE configuration */ > +#define BONITO_IODEVCFG (0x08>> 2) /* 0x108 */ > + > +/* 3. IO& IDE configuration */ > +#define BONITO_SDCFG (0x0c>> 2) /* 0x10c */ > + > +/* 4. PCI address map control */ > +#define BONITO_PCIMAP (0x10>> 2) /* 0x110 */ > +#define BONITO_PCIMEMBASECFG (0x14>> 2) /* 0x114 */ > +#define BONITO_PCIMAP_CFG (0x18>> 2) /* 0x118 */ > + > +/* 5. ICU& GPIO regs */ > +/* GPIO Regs - r/w */ > +#define BONITO_GPIODATA_OFFSET 0x1c > +#define BONITO_GPIODATA (BONITO_GPIODATA_OFFSET>> 2) /* 0x11c */ > +#define BONITO_GPIOIE (0x20>> 2) /* 0x120 */ > + > +/* ICU Configuration Regs - r/w */ > +#define BONITO_INTEDGE (0x24>> 2) /* 0x124 */ > +#define BONITO_INTSTEER (0x28>> 2) /* 0x128 */ > +#define BONITO_INTPOL (0x2c>> 2) /* 0x12c */ > + > +/* ICU Enable Regs - IntEn& IntISR are r/o. */ > +#define BONITO_INTENSET (0x30>> 2) /* 0x130 */ > +#define BONITO_INTENCLR (0x34>> 2) /* 0x134 */ > +#define BONITO_INTEN (0x38>> 2) /* 0x138 */ > +#define BONITO_INTISR (0x3c>> 2) /* 0x13c */ > + > +/* PCI mail boxes */ > +#define BONITO_PCIMAIL0_OFFSET 0x40 > +#define BONITO_PCIMAIL1_OFFSET 0x44 > +#define BONITO_PCIMAIL2_OFFSET 0x48 > +#define BONITO_PCIMAIL3_OFFSET 0x4c > +#define BONITO_PCIMAIL0 (0x40>> 2) /* 0x140 */ > +#define BONITO_PCIMAIL1 (0x44>> 2) /* 0x144 */ > +#define BONITO_PCIMAIL2 (0x48>> 2) /* 0x148 */ > +#define BONITO_PCIMAIL3 (0x4c>> 2) /* 0x14c */ > + > +/* 6. PCI cache */ > +#define BONITO_PCICACHECTRL (0x50>> 2) /* 0x150 */ > +#define BONITO_PCICACHETAG (0x54>> 2) /* 0x154 */ > +#define BONITO_PCIBADADDR (0x58>> 2) /* 0x158 */ > +#define BONITO_PCIMSTAT (0x5c>> 2) /* 0x15c */ > + > +/* 7. other*/ > +#define BONITO_TIMECFG (0x60>> 2) /* 0x160 */ > +#define BONITO_CPUCFG (0x64>> 2) /* 0x164 */ > +#define BONITO_DQCFG (0x68>> 2) /* 0x168 */ > +#define BONITO_MEMSIZE (0x6C>> 2) /* 0x16c */ > + > +#define BONITO_REGS (0x70>> 2) > + > +/* PCI config for south bridge. type 0 */ > +#define BONITO_PCICONF_IDSEL_MASK 0xfffff800 /* [31:11] */ > +#define BONITO_PCICONF_IDSEL_OFFSET 11 > +#define BONITO_PCICONF_FUN_MASK 0x700 /* [10:8] */ > +#define BONITO_PCICONF_FUN_OFFSET 8 > +#define BONITO_PCICONF_REG_MASK 0xFC > +#define BONITO_PCICONF_REG_OFFSET 0 > + > + > +/* idsel BIT = pci slot number +12 */ > +#define PCI_SLOT_BASE 12 > +#define PCI_IDSEL_VIA686B_BIT (17) > +#define PCI_IDSEL_VIA686B (1< + > +#define PCI_ADDR(busno,devno,funno,regno) \ > + ((((busno)<<16)&0xff0000) + (((devno)<<11)&0xf800) + > (((funno)<<8)&0x700) + (regno)) > + > +typedef PCIHostState BonitoState; > + > +typedef struct PCIBonitoState > +{ > + PCIDevice dev; > + BonitoState *pcihost; > + uint32_t regs[BONITO_REGS]; > + > + struct bonldma { > + uint32_t ldmactrl; > + uint32_t ldmastat; > + uint32_t ldmaaddr; > + uint32_t ldmago; > + } bonldma; > + > + /* Based at 1fe00300, bonito Copier */ > + struct boncop { > + uint32_t copctrl; > + uint32_t copstat; > + uint32_t coppaddr; > + uint32_t copgo; > + } boncop; > + > + /* north brige pci config */ > + uint8_t config[256]; > + > + /* Bonito registers */ > + target_phys_addr_t bonito_reg_start; > + target_phys_addr_t bonito_reg_length; > + int bonito_reg_handle; > + > + target_phys_addr_t bonito_pciconf_start; > + target_phys_addr_t bonito_pciconf_length; > + int bonito_pciconf_handle; > + > + target_phys_addr_t bonito_spciconf_start; > + target_phys_addr_t bonito_spciconf_length; > + int bonito_spciconf_handle; > + > + target_phys_addr_t bonito_pciio_start; > + target_phys_addr_t bonito_pciio_length; > + int bonito_pciio_handle; > + > + target_phys_addr_t bonito_localio_start; > + target_phys_addr_t bonito_localio_length; > + int bonito_localio_handle; > + > + target_phys_addr_t bonito_ldma_start; > + target_phys_addr_t bonito_ldma_length; > + int bonito_ldma_handle; > + > + target_phys_addr_t bonito_cop_start; > + target_phys_addr_t bonito_cop_length; > + int bonito_cop_handle; > + > +} PCIBonitoState; > + > +PCIBonitoState * bonito_state; > + > +static void bonito_writeb(void *opaque, target_phys_addr_t addr, uint32_t val) > +{ > + DPRINTF("bonito_writeb "TARGET_FMT_plx" val %x \n", addr, val); > +} > + > +static void bonito_writew(void *opaque, target_phys_addr_t addr, uint32_t val) > +{ > + DPRINTF("bonito_writew "TARGET_FMT_plx" val %x \n", addr, val); > +} > + > +static void bonito_writel(void *opaque, target_phys_addr_t addr, uint32_t val) > +{ > + PCIBonitoState *s = opaque; > + uint32_t saddr; > + int reset = 0; > + > + saddr = (addr - 0x100)>> 2; > + > + DPRINTF("bonito_writel "TARGET_FMT_plx" val %x saddr %x \n", > addr, val, saddr); > Your mailer wraps lines which makes the patch unusable. Try using git send-email.