From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from [140.186.70.92] (port=47011 helo=eggs.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1OGu5S-0001zQ-EE for qemu-devel@nongnu.org; Tue, 25 May 2010 09:22:28 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.69) (envelope-from ) id 1OGu5Q-0006rY-SN for qemu-devel@nongnu.org; Tue, 25 May 2010 09:22:26 -0400 Received: from tx2ehsobe005.messaging.microsoft.com ([65.55.88.15]:46011 helo=TX2EHSOBE010.bigfish.com) by eggs.gnu.org with esmtp (Exim 4.69) (envelope-from ) id 1OGu5Q-0006rP-PK for qemu-devel@nongnu.org; Tue, 25 May 2010 09:22:24 -0400 Message-ID: <4BFBCEEA.4030101@amd.com> Date: Tue, 25 May 2010 15:21:46 +0200 From: Andre Przywara MIME-Version: 1.0 Subject: Re: [Qemu-devel] [PATCH] resent: x86/cpuid: propagate further CPUID leafs when -cpu host References: <1274428240-10801-1-git-send-email-andre.przywara@amd.com> <4BFAF941.1010604@codemonkey.ws> In-Reply-To: <4BFAF941.1010604@codemonkey.ws> Content-Type: text/plain; charset="ISO-8859-1"; format=flowed Content-Transfer-Encoding: 7bit List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Anthony Liguori Cc: "avi@redhat.com" , "aurelien@aurel32.net" , "qemu-devel@nongnu.org" Anthony Liguori wrote: > On 05/21/2010 02:50 AM, Andre Przywara wrote: >> -cpu host currently only propagates the CPU's family/model/stepping, >> the brand name and the feature bits. >> Add a whitelist of safe CPUID leafs to let the guest see the actual >> CPU's cache details and other things. >> >> Signed-off-by: Andre Przywara >> > > The problem I can see is that this greatly increases the chances of > problems with live migration since we don't migrate the cpuid state. I think that should be fixed. Although -cpu host is not a wise choice for migration, even without these additional leaves the feature bits probably don't match between source and target. > What's the benefit of exposing this information to the guest? That is mostly to propagate the cache size and organization parameters to the guest: >> +/* safe CPUID leafs to propagate to guest if -cpu host is specified >> + * Intel defined leafs: >> + * Cache descriptors (0x02) >> + * Deterministic cache parameters (0x04) >> + * Monitor/MWAIT parameters (0x05) >> + * >> + * AMD defined leafs: >> + * L1 Cache and TLB (0x05) >> + * L2+L3 TLB (0x06) >> + * LongMode address size (0x08) >> + * 1GB page TLB (0x19) >> + * Performance optimization (0x1A) >> + */ Since at least L1 and L2 caches are mostly private to vCPUs, I see no reason to disguise them. Regards, Andre. -- Andre Przywara AMD-Operating System Research Center (OSRC), Dresden, Germany Tel: +49 351 448-3567-12