From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from [140.186.70.92] (port=45221 helo=eggs.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1OKcfC-00087H-Ff for qemu-devel@nongnu.org; Fri, 04 Jun 2010 15:34:44 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.69) (envelope-from ) id 1OKcer-0005gl-CA for qemu-devel@nongnu.org; Fri, 04 Jun 2010 15:34:23 -0400 Received: from are.twiddle.net ([75.149.56.221]:55567) by eggs.gnu.org with esmtp (Exim 4.69) (envelope-from ) id 1OKceq-0005g6-L6 for qemu-devel@nongnu.org; Fri, 04 Jun 2010 15:34:21 -0400 Message-ID: <4C095537.50108@twiddle.net> Date: Fri, 04 Jun 2010 12:34:15 -0700 From: Richard Henderson MIME-Version: 1.0 Subject: Re: [Qemu-devel] [PATCH 1/2] tcg: Add TYPE parameter to tcg_out_mov. References: <1275524816-4187-1-git-send-email-rth@twiddle.net> <1275524816-4187-2-git-send-email-rth@twiddle.net> In-Reply-To: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Blue Swirl Cc: qemu-devel@nongnu.org, aurelien@aurel32.net On 06/04/2010 12:19 PM, Blue Swirl wrote: > Sparc32plus would match, though the ABI does not guarantee that higher > 32 bits are preserved. Actually, it does for %g and %o registers. See section 2.1.1. I've thought before about how to adjust the __sparcv8plus__ TCG to use full 64-bit registers and operations when required, but have not yet gotten around to it. All of sparc, mips, ppc, and s390 have a mode with 32-bit pointers running on a machine with 64-bit registers and operations available. Unfortunately the hppa linux kernel doesn't save the full 64-bit register on interrupt, so we're strictly limited to pa1.1 there, even when running on a pa2 machine. Something for the future... r~