From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from [140.186.70.92] (port=57362 helo=eggs.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1ONwWA-000362-UB for qemu-devel@nongnu.org; Sun, 13 Jun 2010 19:23:08 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.69) (envelope-from ) id 1ONwT8-0004RY-Sj for qemu-devel@nongnu.org; Sun, 13 Jun 2010 19:19:59 -0400 Received: from mail-pw0-f45.google.com ([209.85.160.45]:54622) by eggs.gnu.org with esmtp (Exim 4.69) (envelope-from ) id 1ONwT8-0004RJ-Gg for qemu-devel@nongnu.org; Sun, 13 Jun 2010 19:19:58 -0400 Received: by pwj8 with SMTP id 8so2455428pwj.4 for ; Sun, 13 Jun 2010 16:19:57 -0700 (PDT) Sender: Richard Henderson Message-ID: <4C156785.8060900@twiddle.net> Date: Sun, 13 Jun 2010 16:19:33 -0700 From: Richard Henderson MIME-Version: 1.0 Subject: Re: [Qemu-devel] [PATCH 16/35] tcg-s390: Re-implement tcg_out_movi. References: <1275678883-7082-1-git-send-email-rth@twiddle.net> <1275678883-7082-17-git-send-email-rth@twiddle.net> <20100612120443.GM3008@ohm.aurel32.net> In-Reply-To: <20100612120443.GM3008@ohm.aurel32.net> Content-Type: text/plain; charset=ISO-8859-15 Content-Transfer-Encoding: 7bit List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Aurelien Jarno Cc: qemu-devel@nongnu.org, agraf@suse.de On 06/12/2010 05:04 AM, Aurelien Jarno wrote: >> + for (i = 0; i < 4; i++) { >> + tcg_target_long mask = 0xffffull << i*16; >> + if ((uval & mask) != 0 && (uval & ~mask) == 0) { > > Wouldn't it be simpler to use (uval & mask) == uval ? Doh. >> + /* Try for PC-relative address load. */ >> + if ((sval & 1) == 0) { >> + intptr_t off = (sval - (intptr_t)s->code_ptr) >> 1; >> + if (off == (int32_t)off) { >> + tcg_out_insn(s, RIL, LARL, ret, off); >> + return; >> + } >> + } > > Is this part used in practice? There was such a trick on the ARM > backend, but it was actually never used. Yes. The difference here is we have a +- 4GB displacement. This is primarily used when the extended-immediate facility is not present; we can generate all even 32-bit constants from LARL, given the placement of the code_gen_buffer. r~