From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from [140.186.70.92] (port=51137 helo=eggs.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1OnGlW-0007xO-Jj for qemu-devel@nongnu.org; Sun, 22 Aug 2010 16:03:39 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.69) (envelope-from ) id 1OnGlV-00071N-GG for qemu-devel@nongnu.org; Sun, 22 Aug 2010 16:03:38 -0400 Received: from mail-gx0-f173.google.com ([209.85.161.173]:51929) by eggs.gnu.org with esmtp (Exim 4.69) (envelope-from ) id 1OnGlV-00071J-BB for qemu-devel@nongnu.org; Sun, 22 Aug 2010 16:03:37 -0400 Received: by gxk5 with SMTP id 5so2050498gxk.4 for ; Sun, 22 Aug 2010 13:03:36 -0700 (PDT) Message-ID: <4C718296.8030405@codemonkey.ws> Date: Sun, 22 Aug 2010 15:03:34 -0500 From: Anthony Liguori MIME-Version: 1.0 Subject: Re: [Qemu-devel] [PATCH v2 0/7] APIC/IOAPIC cleanup References: <4C6D86F9.3010602@codemonkey.ws> <4C6D98E7.9020109@codemonkey.ws> <4C70EFC9.2050404@redhat.com> <4C7171EB.7090301@codemonkey.ws> <4C717E05.50609@redhat.com> In-Reply-To: <4C717E05.50609@redhat.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Avi Kivity Cc: Blue Swirl , "Liu >> \"Liu, Jinsong\"" , qemu-devel , Paul Brook On 08/22/2010 02:44 PM, Avi Kivity wrote: >> No more MI diamond and all devices have DeviceStates. >> Coincidentally, it matches more closely how hardware works.. >> > > > Well, I agree, but I honestly lost the context. How does this relate > to the APIC and cpu hotplug? My original assertion was that the local APIC is not a DeviceState, but rather it's a CPU feature. If you look at some of the magic that apic.c has to do in the IO callbacks, it should be clear that it's special. In the not too distant future, I'd like to move apic.c to target-i386. There should be no need to explicitly instantiate it when you instantiate a CPU. BTW, this gets a bit funky with KVM. If we declare that the lapic is part of the CPU, then in an ideal world we would have interfaces for the I/O APIC as part of the KVM interface so we could implement the I/O APIC in userspace with the lapic implemented in the kernel. Regards, Anthony Liguori