From: Alexander Graf <agraf@suse.de>
To: Thomas Monjalon <thomas.monjalon@openwide.fr>
Cc: Bug 608107 <608107@bugs.launchpad.net>, qemu-devel@nongnu.org
Subject: Re: [Qemu-devel] [PATCH] target-ppc: clear MSR_POW on interrupt
Date: Fri, 10 Sep 2010 15:02:41 +0200 [thread overview]
Message-ID: <4C8A2C71.6040604@suse.de> (raw)
In-Reply-To: <201009101432.06340.thomas.monjalon@openwide.fr>
Thomas Monjalon wrote:
> From: till <608107@bugs.launchpad.net>
>
> According to FreeScale's 'Programming Environments Manual for 32-bit
> Implementations of the PowerPC Architecture' [MPCFPE32B, Rev.3, 9/2005],
> section 6.5, table 6-7, an interrupt resets MSR_POW to zero but qemu-0.12.4
> fails to do so.
> Resetting the bit is necessary in order to bring the processor out of power
> management since otherwise it goes to sleep right away in the exception
> handler, i.e., it is impossible to leave PM-mode.
>
This doesn't look right. POW shouldn't even get stored in SRR1. Could
you please redo the patch and make sure that mtmsr masks out MSR_POW?
Alex
next prev parent reply other threads:[~2010-09-10 13:02 UTC|newest]
Thread overview: 17+ messages / expand[flat|nested] mbox.gz Atom feed top
2010-07-21 8:53 [Qemu-devel] [Bug 608107] [NEW] ppc fails to clear MSR_POW when incurring exception till
2010-07-21 8:53 ` [Qemu-devel] [Bug 608107] " till
2010-09-10 12:32 ` [Qemu-devel] [PATCH] target-ppc: clear MSR_POW on interrupt Thomas Monjalon
2010-09-10 13:02 ` Alexander Graf [this message]
2010-09-10 15:03 ` Thomas Monjalon
2010-09-10 15:26 ` Alexander Graf
2010-09-10 15:46 ` Thomas Monjalon
2010-09-10 15:50 ` Alexander Graf
2010-09-10 16:08 ` Edgar E. Iglesias
2010-09-10 16:35 ` Alexander Graf
2010-09-10 16:58 ` Thomas Monjalon
2010-09-10 19:57 ` Edgar E. Iglesias
2010-09-10 23:10 ` Alexander Graf
2010-09-10 9:22 ` [Qemu-devel] [Bug 608107] Re: ppc fails to clear MSR_POW when incurring exception Thomas Monjalon
2010-09-13 13:02 ` till
2012-08-03 2:56 ` Samuel Bronson
2016-10-31 9:11 ` Thomas Huth
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