From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from [140.186.70.92] (port=46080 helo=eggs.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1OwaWc-0007h1-Hs for qemu-devel@nongnu.org; Fri, 17 Sep 2010 08:58:48 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.69) (envelope-from ) id 1OwaRU-0007AH-IJ for qemu-devel@nongnu.org; Fri, 17 Sep 2010 08:53:29 -0400 Received: from e6.ny.us.ibm.com ([32.97.182.146]:60554) by eggs.gnu.org with esmtp (Exim 4.69) (envelope-from ) id 1OwaRU-0007A8-Ee for qemu-devel@nongnu.org; Fri, 17 Sep 2010 08:53:28 -0400 Received: from d01relay02.pok.ibm.com (d01relay02.pok.ibm.com [9.56.227.234]) by e6.ny.us.ibm.com (8.14.4/8.13.1) with ESMTP id o8HCrQdu019989 for ; Fri, 17 Sep 2010 08:53:26 -0400 Received: from d03av05.boulder.ibm.com (d03av05.boulder.ibm.com [9.17.195.85]) by d01relay02.pok.ibm.com (8.13.8/8.13.8/NCO v10.0) with ESMTP id o8HCrOF2479244 for ; Fri, 17 Sep 2010 08:53:24 -0400 Received: from d03av05.boulder.ibm.com (loopback [127.0.0.1]) by d03av05.boulder.ibm.com (8.14.4/8.13.1/NCO v10.0 AVout) with ESMTP id o8HCrOUj026677 for ; Fri, 17 Sep 2010 06:53:24 -0600 Message-ID: <4C9364B8.6030708@linux.vnet.ibm.com> Date: Fri, 17 Sep 2010 07:53:12 -0500 From: Anthony Liguori MIME-Version: 1.0 Subject: Re: [Qemu-devel] [PATCH] add 40-48 bit RAM range to seabios References: <20100915171528.GO5981@random.random> <20100917014731.GA27371@morn.localdomain> In-Reply-To: <20100917014731.GA27371@morn.localdomain> Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Kevin O'Connor Cc: Andrea Arcangeli , seabios@seabios.org, qemu-devel@nongnu.org, Gleb Natapov On 09/16/2010 08:47 PM, Kevin O'Connor wrote: > On Wed, Sep 15, 2010 at 07:15:28PM +0200, Andrea Arcangeli wrote: > >> Subject: add 40-48 bit RAM range to seabios >> >> From: Andrea Arcangeli >> >> Needed to show>1TB RAM to guests. >> >> This uses a new cmos port at 0x5e that shall read zero to be backwards >> compatible. >> >> Signed-off-by: Andrea Arcangeli >> > It looks okay to me. Can you provide an Acked-by from one of the qemu > or kvm maintainers? > Is CMOS the best place to communicate this (as opposed to fw_cfg)? I know we currently expose memory size via CMOS but perhaps it's better to switch to a 64-bit fw_cfg value. Regards, Anthony Liguori > -Kevin >