[Qemu-devel] sparc OBP psr value

[Qemu-devel] sparc OBP psr value

[Bob Breuer]

Under qemu-system-sparc, I found a problem with OBP's psr commands.

On an real SS-20, I get:
    ok .psr
    CWP: 4  ET: 1  PS: 1  S: 1  PIL: f  EF: 1  EC: 0  ICC: nZvc  VER: 0 
IMPL: 4
    ok %psr .
    40401fe4
But with qemu, it all shows up as 0, such as:
    ok .psr
    CWP: 0  ET: 0  PS: 0  S: 0  PIL: 0  EF: 0  EC: 0  ICC: nzvc  VER: 0 
IMPL: 0
    ok %psr .
    0
while "info registers" says the psr should be 40001de0.

Any suggestion of how to debug this?

Bob

[Qemu-devel] Re: sparc OBP psr value

[Blue Swirl]

On Sun, Dec 12, 2010 at 12:17 AM, Bob Breuer <breuerr@mc.net> wrote:
> Under qemu-system-sparc, I found a problem with OBP's psr commands.
>
> On an real SS-20, I get:
>    ok .psr
>    CWP: 4  ET: 1  PS: 1  S: 1  PIL: f  EF: 1  EC: 0  ICC: nZvc  VER: 0
> IMPL: 4
>    ok %psr .
>    40401fe4
> But with qemu, it all shows up as 0, such as:
>    ok .psr
>    CWP: 0  ET: 0  PS: 0  S: 0  PIL: 0  EF: 0  EC: 0  ICC: nzvc  VER: 0
> IMPL: 0
>    ok %psr .
>    0
> while "info registers" says the psr should be 40001de0.

I can't reproduce this:
ok .psr
CWP: 0  ET: 1  PS: 1  S: 1  PIL: f  EF: 0  EC: 0  ICC: nZvc  VER: 0  IMPL: 4
ok %psr .
40400fe0

Re: [Qemu-devel] Re: sparc OBP psr value

[Bob Breuer]

Blue Swirl wrote:
> On Sun, Dec 12, 2010 at 12:17 AM, Bob Breuer <breuerr@mc.net> wrote:
>   
>> Under qemu-system-sparc, I found a problem with OBP's psr commands.
>>
>> On an real SS-20, I get:
>>    ok .psr
>>    CWP: 4  ET: 1  PS: 1  S: 1  PIL: f  EF: 1  EC: 0  ICC: nZvc  VER: 0
>> IMPL: 4
>>    ok %psr .
>>    40401fe4
>> But with qemu, it all shows up as 0, such as:
>>    ok .psr
>>    CWP: 0  ET: 0  PS: 0  S: 0  PIL: 0  EF: 0  EC: 0  ICC: nzvc  VER: 0
>> IMPL: 0
>>    ok %psr .
>>    0
>> while "info registers" says the psr should be 40001de0.
>>     
>
> I can't reproduce this:
> ok .psr
> CWP: 0  ET: 1  PS: 1  S: 1  PIL: f  EF: 0  EC: 0  ICC: nZvc  VER: 0  IMPL: 4
> ok %psr .
> 40400fe0
>   

Ah, I forget to verify it with the SS-20 default cpu where it does
indeed work, but in that case OBP gets an access fault which leaves it
only partially initialized.

For me, either OBP under SS-5 with it's default cpu, or SS-20 with
SuperSparc 60 both show the failure.  The most obvious is SS-20 with
Ross RT625 where it misdetects the cpu as a 605e.

This is with a 32-bit x86 host (both Debian 5.0.7 and win32).

Bob

Re: [Qemu-devel] Re: sparc OBP psr value

[Bob Breuer]

Forget this.  My test was flawed because I still wasn't comparing apples
to apples.  I was comparing the pre-bootloader state to the
post-bootloader state, and it seems that OBP, even on a real machine,
shows all the registers as zero before it runs any program.

However, I still think there's something wrong with the RT625 version
somewhere that causes it to show as a 605e in the banner, but I don't
have the real thing to compare against.  What I do have for comparison
is a 150MHz hyperSparc which shows up as an RT626.

Bob