From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from [140.186.70.92] (port=42680 helo=eggs.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1Pc4AP-0002L5-3Z for qemu-devel@nongnu.org; Sun, 09 Jan 2011 17:55:17 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1Pc4AO-0008KW-5m for qemu-devel@nongnu.org; Sun, 09 Jan 2011 17:55:16 -0500 Received: from mail-iw0-f173.google.com ([209.85.214.173]:37369) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Pc4AO-0008KM-2n for qemu-devel@nongnu.org; Sun, 09 Jan 2011 17:55:16 -0500 Received: by iwn40 with SMTP id 40so20274733iwn.4 for ; Sun, 09 Jan 2011 14:55:15 -0800 (PST) Sender: Richard Henderson Message-ID: <4D2A3CD1.2050003@twiddle.net> Date: Sun, 09 Jan 2011 14:55:13 -0800 From: Richard Henderson MIME-Version: 1.0 Subject: Re: [Qemu-devel] Re: [PATCH 5/7] tcg-i386: Implement deposit operation. References: <1294440183-885-1-git-send-email-rth@twiddle.net> <1294440183-885-6-git-send-email-rth@twiddle.net> <20110109215335.GA21189@volta.aurel32.net> In-Reply-To: <20110109215335.GA21189@volta.aurel32.net> Content-Type: text/plain; charset=ISO-8859-15 Content-Transfer-Encoding: 7bit List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Aurelien Jarno Cc: qemu-devel@nongnu.org, Alexander Graf On 01/09/2011 01:53 PM, Aurelien Jarno wrote: >> + if (inout == val) { >> + TCGType type = rexw ? TCG_TYPE_I64 : TCG_TYPE_I32; >> + TCGRegSet inuse = s->reserved_regs; >> + >> + tcg_regset_set_reg(inuse, inout); >> + val = tcg_reg_alloc(s, tcg_target_available_regs[type], inuse); >> + >> + tcg_out_mov(s, type, val, inout); > > I am a bit worried by allocating a new register here, especially on the > i386 target, where the number of free registers is quite low, and often > 0. We already had to tweak some code to avoid calls to tcg_abort() due > to missing registers. Well, as I said, this case can't actually trigger due to a bug in the register allocator. This can be seen in an insn like mov %dl,%dh where you would expect to see deposit x,x,x,8,8 however, the matching constraint forces the destination and the matching source into a new register: /* if the input is aliased to an output and if it is not dead after the instruction, we must allocate a new register and move it */ if (!IS_DEAD_IARG(i - nb_oargs)) goto allocate_in_reg; which means that we'll always see mov y,x deposit y,y,x,8,8 So I could simply put a tcg_abort there. It would be up to whoever improves the register allocator to provide some mechanism for a backend to allocate a scratch. What do you think? r~