From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from [140.186.70.92] (port=58653 helo=eggs.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1Pn90z-00015b-28 for qemu-devel@nongnu.org; Wed, 09 Feb 2011 07:19:23 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1Pn90w-0003yV-Ew for qemu-devel@nongnu.org; Wed, 09 Feb 2011 07:19:19 -0500 Received: from eu1sys200aog113.obsmtp.com ([207.126.144.135]:57621) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Pn90w-0003yL-76 for qemu-devel@nongnu.org; Wed, 09 Feb 2011 07:19:18 -0500 Received: from zeta.dmz-eu.st.com (ns2.st.com [164.129.230.9]) by beta.dmz-eu.st.com (STMicroelectronics) with ESMTP id B190411D for ; Wed, 9 Feb 2011 12:19:16 +0000 (GMT) Received: from Webmail-eu.st.com (safex1hubcas5.st.com [10.75.90.71]) by zeta.dmz-eu.st.com (STMicroelectronics) with ESMTP id 9CBA525BA for ; Wed, 9 Feb 2011 12:19:16 +0000 (GMT) Message-ID: <4D528643.4080106@st.com> Date: Wed, 9 Feb 2011 13:19:15 +0100 From: Christophe Lyon MIME-Version: 1.0 Content-Type: text/plain; charset="ISO-8859-1" Content-Transfer-Encoding: 7bit Subject: [Qemu-devel] [PATCH v2] target-arm: fix VSHLL Neon instruction. List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: "qemu-devel@nongnu.org" Fix bit mask used when widening the result of shift on narrow input. Signed-off-by: Christophe Lyon --- target-arm/translate.c | 18 +++++++++++++++--- 1 files changed, 15 insertions(+), 3 deletions(-) diff --git a/target-arm/translate.c b/target-arm/translate.c index b694eed..16c61f1 100644 --- a/target-arm/translate.c +++ b/target-arm/translate.c @@ -4882,16 +4882,28 @@ static int disas_neon_data_insn(CPUState * env, DisasContext *s, uint32_t insn) /* The shift is less than the width of the source type, so we can just shift the whole register. */ tcg_gen_shli_i64(cpu_V0, cpu_V0, shift); + /* Widen the result of shift: we need to clear + * the potential overflow bits resulting from + * left bits of the narrow input appearing as + * right bits of left the neighbour narrow + * input. */ if (size < 2 || !u) { uint64_t imm64; if (size == 0) { imm = (0xffu >> (8 - shift)); imm |= imm << 16; - } else { + } else if (size == 1) { imm = 0xffff >> (16 - shift); + } else { + /* size == 2 */ + imm = 0xffffffff >> (32 - shift); + } + if (size < 2) { + imm64 = imm | (((uint64_t)imm) << 32); + } else { + imm64 = imm; } - imm64 = imm | (((uint64_t)imm) << 32); - tcg_gen_andi_i64(cpu_V0, cpu_V0, imm64); + tcg_gen_andi_i64(cpu_V0, cpu_V0, ~imm64); } } neon_store_reg64(cpu_V0, rd + pass); -- 1.7.2.3