From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from [140.186.70.92] (port=46492 helo=eggs.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1Q8WJ6-0001hx-9F for qemu-devel@nongnu.org; Sat, 09 Apr 2011 07:26:25 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1Q8WJ5-0000T5-0e for qemu-devel@nongnu.org; Sat, 09 Apr 2011 07:26:24 -0400 Received: from fmmailgate02.web.de ([217.72.192.227]:48282) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Q8WJ4-0000T0-Jz for qemu-devel@nongnu.org; Sat, 09 Apr 2011 07:26:22 -0400 Message-ID: <4DA0424F.5020101@web.de> Date: Sat, 09 Apr 2011 13:26:07 +0200 From: Jan Kiszka MIME-Version: 1.0 References: <20110403195314.GB23034@volta.aurel32.net> <20110403234207.GD11748@valinux.co.jp> <20110404021511.GF11748@valinux.co.jp> <4DA01AF2.3040309@web.de> <20110409110549.GA23309@valinux.co.jp> <4DA040A3.2070309@web.de> In-Reply-To: <4DA040A3.2070309@web.de> Content-Type: multipart/signed; micalg=pgp-sha1; protocol="application/pgp-signature"; boundary="------------enig88AF0AC8F306BB2C632FB42A" Sender: jan.kiszka@web.de Subject: [Qemu-devel] Re: [PATCH] ioapic: Do not set irr for masked edge IRQs List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Isaku Yamahata Cc: qemu-devel@nongnu.org, Aurelien Jarno , kvm This is an OpenPGP/MIME signed message (RFC 2440 and 3156) --------------enig88AF0AC8F306BB2C632FB42A Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable On 2011-04-09 13:18, Jan Kiszka wrote: > On 2011-04-09 13:05, Isaku Yamahata wrote: >> On Sat, Apr 09, 2011 at 10:38:10AM +0200, Jan Kiszka wrote: >>> On 2011-04-04 04:15, Isaku Yamahata wrote: >>>> On Mon, Apr 04, 2011 at 08:42:07AM +0900, Isaku Yamahata wrote: >>>>>> Thank you for applying. But I found that the patch is wrong and >>>>>> I'm preparing the new one. Can you please revert it? >>>> Here is the corrected patch. The first wrong patch clears the interr= upts >>>> bit unconditionally. Which caused losing interrupt. >>>> >>>> From 5ed177d35ab14f3b070a0eba2c49400279a3a14b Mon Sep 17 00:00:00 20= 01 >>>> Message-Id: <5ed177d35ab14f3b070a0eba2c49400279a3a14b.1301883258.git= =2Eyamahata@valinux.co.jp> >>>> In-Reply-To: >>>> References: >>>> From: Isaku Yamahata >>>> Date: Wed, 16 Mar 2011 14:00:13 +0900 >>>> Subject: [PATCH 01/30] ioapic: when switches to level trigger mode, = interrupts raised repeatedly. >>>> >>>> - the trigger mode is edge at first by reset. >>>> - During initializatoin, the interrupt is raised as edge which is ma= sked. >>>> The corresponding bit of irr is set. >>> >>> ...and that is the actual problem. The spec says: "Interrupt Mask?R/W= =2E >>> When this bit is 1, the interrupt signal is masked. Edge-sensitive >>> interrupts signaled on a masked interrupt pin are ignored (i.e., not >>> delivered or held pending)." >>> >>> So this should do the trick in a correct way (untested, please >>> validate): >> >> Thank you for referring the spec. It works. >> Here's the updated patch with your signed-off-by and my tested-by. >=20 > Thanks for testing. I would prefer the following more compact wordings.= >=20 > Jan >=20 > ---------8<---------- >=20 > From: Jan Kiszka >=20 > So far we set IRR for edge IRQs even if the pin is masked. If the guest= > later on unmasks and switches the pin to level-triggered mode, irr will= > remain set, causing an IRQ storm. The point is that setting IRR is not > correct in this case according to the spec, and avoiding this resolves > the issue. >=20 > Reported-and-tested-by: Isaku Yamahata > Signed-off-by: Jan Kiszka > --- > hw/ioapic.c | 5 +++-- > 1 files changed, 3 insertions(+), 2 deletions(-) >=20 > diff --git a/hw/ioapic.c b/hw/ioapic.c > index 569327d..6c26e82 100644 > --- a/hw/ioapic.c > +++ b/hw/ioapic.c > @@ -160,8 +160,9 @@ static void ioapic_set_irq(void *opaque, int vector= , int level) > s->irr &=3D ~mask; > } > } else { > - /* edge triggered */ > - if (level) { > + /* According to the 82093AA manual, we must ignore edge re= quests > + * if the input pin is masked. */ > + if (level && !(entry & IOAPIC_LVT_MASKED)) { > s->irr |=3D mask; > ioapic_service(s); > } On first glance, it looks like KVM's in-kernel IOAPIC model is affected by the same issue. As you have the test case at hand, could you run it against qemu-kvm which stresses the kernel version? TIA, Jan --------------enig88AF0AC8F306BB2C632FB42A Content-Type: application/pgp-signature; name="signature.asc" Content-Description: OpenPGP digital signature Content-Disposition: attachment; filename="signature.asc" -----BEGIN PGP SIGNATURE----- Version: GnuPG v2.0.15 (GNU/Linux) Comment: Using GnuPG with SUSE - http://enigmail.mozdev.org/ iEYEARECAAYFAk2gQlIACgkQitSsb3rl5xQnNgCgoAMpM8X+3Wvytj/Zq1CklYWp GSYAn0XJpO73RdfYC5xCMBg7LhPA7inN =flX/ -----END PGP SIGNATURE----- --------------enig88AF0AC8F306BB2C632FB42A--