From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([140.186.70.92]:40293) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1QAPOB-0006Ja-T3 for qemu-devel@nongnu.org; Thu, 14 Apr 2011 12:27:28 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1QAPOB-00070F-0t for qemu-devel@nongnu.org; Thu, 14 Apr 2011 12:27:27 -0400 Received: from a.mail.sonic.net ([64.142.16.245]:33886) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1QAPOA-0006zw-Oy for qemu-devel@nongnu.org; Thu, 14 Apr 2011 12:27:26 -0400 Message-ID: <4DA7205E.1070208@twiddle.net> Date: Thu, 14 Apr 2011 09:27:10 -0700 From: Richard Henderson MIME-Version: 1.0 References: <1302645571-20500-1-git-send-email-aurelien@aurel32.net> <1302645571-20500-9-git-send-email-aurelien@aurel32.net> <4DA5C372.5090807@twiddle.net> <4DA70F43.90701@twiddle.net> In-Reply-To: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit Subject: Re: [Qemu-devel] [PATCH 08/19] target-alpha: use new float64_unordered() function List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Peter Maydell Cc: qemu-devel@nongnu.org, Aurelien Jarno On 04/14/2011 08:39 AM, Peter Maydell wrote: >> Exponent underflow and disabled: >> Supply +0, no exception delivered to user. >> >> Exponent underflow and enabled: >> Supply +-MIN denorm, Underflow delivered to user. >> >> Footnote 3, Overflow and Underflow have priority over Inexact. > > Thanks. Does "no exception delivered to user" mean also > "and do not set FPCR bit UNF" ? Yes. > The reason I thought it might set Inexact is that I was looking > at page 4-79, which says: > > "If both the UNFD (underflow disable) bit and the UNDZ (underflow > to zero) bit are set in the FPCR, the implementation sets the > result of an underflow operation to a true zero result. The > zeroing of a denormal result by UNDZ must also be treated as an > inexact result." Hum. It looks like we can choose between these results then, depending on the intersection of the FPCR disable bits, and the per-instruction trapping mode bits (see section 4.7.7.2). I *think* what would be best for Alpha is if, within softfloat, both conditions are signaled, and then we can filter the result that is actually needed via helper_fp_exc_raise? It's hard to say without actually doing the work... Unfortunately, I suspect that the Correct result on real HW also depends on the OS completion handler, and I know that at least for Linux that code was written before UNDZ was added. So I don't know if even real HW produces the correct result when considering Underflow priority over Inexact. r~